View PXB4350E_712816.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICs for Communications
ATM OAM Processor AOP PXB 4340 E Version 1.1
Data Sheet 04.2000 DS 1
3;% ( 5HYLVLRQ +LVWRU\ &XUUHQW 9HUVLRQ Previous Version: Preliminary Data Sheet 09.98 (DS 2) Page Page Subjects (major changes since last revision) (in previous (in current Version) Version) The Data Sheet has been reorganized.
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.Infineon.com.
IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R) , ARCOFI(R)-BA,
ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Infineon Technologies AG. MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, DigiTapeTM are trademarks of Infineon Technologies AG. All other brand or product names, Hardware or Software names are trademarks or registered trademarks of their respective companies or organizations.
(GLWLRQ This edition was realized using the software system FrameMaker(R). 3XEOLVKHG E\ ,QILQHRQ 7HFKQRORJLHV $* 6& %DODQVWUDH 0QFKHQ (c) Infineon Technologies AG 2000. All Rights Reserved. $WWHQWLRQ SOHDVH As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Infineon Technologies Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. 3DFNLQJ Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. &RPSRQHQWV XVHG LQ OLIHVXSSRUW GHYLFHV RU V\VWHPV PXVW EH H[SUHVVO\ DXWKRUL]HG IRU VXFK SXUSRVH Critical components1 of Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
3;% (
7DEOH RI &RQWHQWV 3DJH
1.1 1.2 1.3 1.4 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.7.1 2.7.2 2.8 2.8.1 2.8.1.1 2.8.1.2 2.8.1.3 2.8.1.4 2.9 2.9.1 2.9.2 2.9.3 2.9.4 2.9.5 2.10 2.11 2.12 2.12.1 2.12.2 2.13 2.14 2.15 2.16 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.2 3.2.1 3.2.2
Data Sheet
2YHUYLHZ Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Layer Point Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 )XQFWLRQDO 'HVFULSWLRQ Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Cell Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Cell Buffering and OAM Cell Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Addressing of external RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 OAM Functions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Alarm OAM Functions (AIS/RDI/CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Transmission Line Failures (AIS/RDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ATM Layer Failures (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Network Connectivity Check (LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 F4/F5 End-to-End Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 F4/F5 Segment Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 F4/F5 End Point Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 VPCI Consistency Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Connection Quality Measurement (PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PM Data Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Simultaneous PM flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Adjacent PM Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Activation and Deactivation Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Interactions between OAM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Cell Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Special OAM Cell Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 General purpose Cell Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Microprocessor Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Access to internal and external RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SCAN Mechanism with OAM and/or DMA Function . . . . . . . . . . . . . . . . . . . . . . 48 Receive and Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5HJLVWHU 'HVFULSWLRQ Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Write Transfer Registers (WDR0L..WDR13H) . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Read Transfer Registers (RDR0L..RDR13H) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Mask Data Registers (MDR0L..MDR6H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Write Mask Register (WMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Read-Modify-Write Control Register (RMWC) . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Read-Modify-Write Address Register (RMWADR) . . . . . . . . . . . . . . . . . . . . . . . 63 Registers for Celltype Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Location / Source Identifier Registers (LSIDR0..7) . . . . . . . . . . . . . . . . . . . . . . . 64 Special OAM Cell Filter (CTR0, CTR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
0-3 04.2000
3;% (
7DEOH RI &RQWHQWV 3DJH
3.2.3 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.5.10 3.5.11 3.5.12 3.5.13 3.5.14 3.5.15 3.5.16 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.7.6 3.7.7 3.8 3.8.1
Data Sheet
Cell Filter 1 and 2 Registers (CTRxy, MRxy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Transmit / Receive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Transmit Cell Header Registers (TXR0..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Transmit Cell Payload Registers (TXR3..TXR26) . . . . . . . . . . . . . . . . . . . . . . 68 Transmission Command Register (TMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Receive Cell Buffer Read Register (RXRCEL) . . . . . . . . . . . . . . . . . . . . . . . . 70 Performance Monitoring Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 71 Upstream Maximum Lost cells (UMLOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Upstream Maximum Misinserted cells (UMMISINS) . . . . . . . . . . . . . . . . . . . . 71 Upstream Maximum Lost CLP0 cells (UMLOST0) . . . . . . . . . . . . . . . . . . . . . . . 71 Upstream Maximum Errors (UMERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Downstream Maximum Lost cells (DMLOST) . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Downstream Maximum Misinserted cells (DMMISINS) . . . . . . . . . . . . . . . . . . . 72 Downstream Maximum Lost CLP0 cells (DMLOST0) . . . . . . . . . . . . . . . . . . . . 72 Downstream Maximum Errors (DMERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Scan Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 DMA Write Register 15..0 (DWDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DMA Write Register 31..16 (DWDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DMA Mask Register 15..0 (DMRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DMA Mask Register High 31..16 (DMRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PHY Error Indication 15..0 (PHYERRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 PHY Error Indication 23..16 (PHYERRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DMA Read Register (DMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DMA Configuration Register (DCONF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Time Constant Register 0 (SCCONF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Time Constant Register 1 (SCCONF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Time Constant Register 2 (SCCONF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SCAN Command Register (SCCONF3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Lower Boundary of LCI Range (SCCONF4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Upper Boundary of LCI Range (SCCONF5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 SCAN Status Register (SCSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Currently Processed LCI (SCSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Interrupt and Interrupt Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Interrupt Status Register 0 (ISR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Interrupt Status Register 1 (ISR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Interrupt Mask Register 0 (IMR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Interrupt Mask Register 1 (IMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Cell Insertion Fault Register low and high (CIFL and CIFH) . . . . . . . . . . . . . . . 85 UTOPIA Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 UTOPIA Configuration Register 0 (UTCONF0) . . . . . . . . . . . . . . . . . . . . . . . . . 87 UTOPIA Configuration Register 1 (UTCONF1) . . . . . . . . . . . . . . . . . . . . . . . . . 88 Upstream Port Enable low and high (UPRTENL and UPRTENH) . . . . . . . . . . . 89 Downstream Port Enable low and high (DPRTENL and DPRTENH) . . . . . . . . . 89 OAM Cell Insertion Threshold Upstream (OAMTHRU) . . . . . . . . . . . . . . . . . . . 90 OAM Cell Insertion Threshold Downstream (OAMTHRD) . . . . . . . . . . . . . . . . . 91 Backpressure Threshold Downstream (BPTHRD) . . . . . . . . . . . . . . . . . . . . . . . 91 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 RAM Type Select Register (MISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
0-4 04.2000
3;% (
7DEOH RI &RQWHQWV 3DJH
3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 3.8.8 3.9 3.9.1 3.9.1.1 3.9.1.2 3.9.1.3 3.9.1.4 3.9.2 3.9.2.1 3.9.2.2 3.9.2.3 3.9.2.4 3.9.3 3.9.3.1 3.9.3.2 3.9.3.3 3.9.3.4 3.9.4 3.9.4.1 3.9.4.2 3.9.4.3 3.9.4.4 3.9.5 3.9.5.1 3.9.5.2 3.9.5.3 3.9.6 3.9.6.1 3.9.6.2 3.9.6.3 3.9.6.4 3.9.6.5 3.9.6.6 3.9.6.7 3.9.6.8 3.9.6.9 3.9.6.10 3.9.6.11 3.9.6.12 3.9.6.13 3.9.6.14
Test Register 1 (TESTR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Test Register 2 (TESTR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Version Register low and high (VERL and VERH) . . . . . . . . . . . . . . . . . . . . . . . 94 BIST Mode Register Low (BISTML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 BIST Mode Register High (BISTMH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 BIST Done Register (BISTDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 BIST Error Register (BISTERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 External and Internal RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Upstream External RAM F5 Entry: Dwords 0..3 . . . . . . . . . . . . . . . . . . . . . . . . . 98 Upstream F5 OAM Entry: Dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Upstream F5 OAM Entry: Dword1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Upstream F5 OAM Entry: Dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Upstream F5 OAM Entry: Dword3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Upstream External RAM F4 Entry: Dwords 4..7 . . . . . . . . . . . . . . . . . . . . . . . . 104 Upstream F4 OAM entry: Dword4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Upstream F4 OAM Entry: Dword5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Upstream F4 OAM Entry : Dword6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Upstream F4 OAM Entry: Dword7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Downstream External RAM F5 Entry: Dwords 0..3 . . . . . . . . . . . . . . . . . . . . 110 Downstream F5 OAM Entry: Dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Downstream F5 OAM Entry: Dword1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Downstream F5 OAM Entry: Dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Downstream F5 OAM Entry: Dword3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Downstream External RAM F4 Entry: Dwords 4..7 . . . . . . . . . . . . . . . . . . . . 116 Downstream F4 OAM Entry: Dword4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Downstream F4 OAM Entry: Dword5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Downstream F4 OAM Entry: Dword6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Downstream F4 OAM Entry: Dword7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Internal PM Main RAM Entry: Dwords 0..2 . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Internal PM Main RAM Entry: Dword 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Internal PM Main RAM Entry: Dword 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Internal PM Main RAM Entry: Dword 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Internal PM Data Collection RAM Entry: Dwords 0..13 . . . . . . . . . . . . . . . . . 123 Internal PM Data Collection RAM Entry: Dword 0 . . . . . . . . . . . . . . . . . . . . . 123 Internal PM Data Collection RAM Entry: Dword 1 . . . . . . . . . . . . . . . . . . . . . 123 Internal PM Data Collection RAM Entry: Dword 2 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 3 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 4 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 5 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 6 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 7 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 8 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 9 . . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 10 . . . . . . . . . . . . . . . . . . . . 124 Internal PM Data Collection RAM Entry: Dword 11 . . . . . . . . . . . . . . . . . . . . 125 Internal PM Data Collection RAM Entry: Dword 12 . . . . . . . . . . . . . . . . . . . . 125 Internal PM Data Collection RAM Entry: Dword 13 . . . . . . . . . . . . . . . . . . . . 125
Data Sheet
0-5
04.2000
3;% (
7DEOH RI &RQWHQWV 3DJH
4.1 4.1.1 4.1.1.1 4.1.1.2 4.1.1.3 4.1.1.4 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.6.1 4.1.6.2 4.1.7 4.1.7.1 4.1.7.2 4.1.7.3 4.1.7.4 4.2 4.2.1 5.1 5.1.1 5.2 5.3 5.4 5.5 5.6 6.1 6.2 6.3 6.4 6.4.1 6.4.1.1 6.4.1.2 6.4.1.3 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.5 6.6
2SHUDWLRQ Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Guidelines for microprocessor actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Write-Modify-Read-Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Cell insertion by the microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Reading of arrived cells by the microprocessor . . . . . . . . . . . . . . . . . . . . . . . . 127 SCAN usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Initialization and Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Setup/ Cleardown of Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Enable/ Disable of PM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Scan Process Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 PM Threshold Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Transmission Line Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 LB Cell Transmission/ Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 PM Activation/ Deactivation Cell Transmission . . . . . . . . . . . . . . . . . . . . . . . . 132 PM Activation/ Deactivation Cell Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 PM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ,QWHUIDFHV UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 UTOPIA Multi-PHY support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 RAM Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 JTAG/Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 (OHFWULFDO &KDUDFWHULVWLFV Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Microprocessor Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Microprocessor Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 DMA Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 SSRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Cell Filter Detector Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Boundary-Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 3DFNDJH 2XWOLQHV
Data Sheet
0-6
04.2000
3;% (
7DEOH RI &RQWHQWV 3DJH
8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.3 8.4
2YHUYLHZ /LVWV Layer Point Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 OAM Cell Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 OAM Cell Header Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 AIS Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 RDI Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 CC Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 LB Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 FM Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 BR Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 PM/CC Activation/deactivation Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Data Sheet
0-7
04.2000
3;% (
/LVW RI )LJXUHV 3DJH
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46:
Data Sheet
Chipset configuration for main ATM layer functionality . . . . . . . . . . . . . . . . . . . 11 Chipset configuration for main ATM layer functionality plus full OAM . . . . . . . . 12 Chipset configuration for main ATM layer functionality plus full OAM and arbitrary header translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Miniswitch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Line card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Location of PXB 4340 E AOP on a Switch Port . . . . . . . . . . . . . . . . . . . . . . . . . 18 Symbol for Switch with AOPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VP Level OAM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VC Level OAM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VC Endpoint inside the Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cell Buffers in PXB 4340 AOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thresholds in UTOPIA cell buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pointer Structure of up- and downstream OAM Tables . . . . . . . . . . . . . . . . . . . 26 Example for Line Failure Notification via AIS cells . . . . . . . . . . . . . . . . . . . . . . . 28 VP-AIS/RDI-Flow (F4-AIS/RDI-Flow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AIS State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 RDI State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Example for Misrouting Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 F4 segment CC Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Continuity Check Cell Generation State Diagram . . . . . . . . . . . . . . . . . . . . . . . 33 Continuity Check Evaluation State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Example of F4 End-to-End Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . 36 Example of F5 Segment Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . . . 37 Example of F4 End Point Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . . 38 PM Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PM Data Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Example for adjacent PM Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Effect of CC cells on AIS recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Access to internal or external RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Scan Mechanism with OAM and/or DMA Function . . . . . . . . . . . . . . . . . . . . . . 49 Read-modify-write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Performance Monitoring Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Standardized UTOPIA cell format (16-bit) all fields according to standards, unused octets shaded . . . . . . . . . . . . . . . . . 136 Proprietary UTOPIA cell format (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Upstream receive UTOPIA example for 4 x 6 PHYs . . . . . . . . . . . . . . . . . . . . 137 Upstream or downstream RAM interface using 2 Mbits RAMs . . . . . . . . . . . . 139 Upstream or downstream RAM Interface using 1 Mbit RAMs . . . . . . . . . . . . . 140 Example of Execution Timing for Read Cycles (Burst Mode) . . . . . . . . . . . . . . 141 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . . . . . . . . . 153 Microprocessor Interface Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Microprocessor Interface Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Microprocessor DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
0-8 04.2000
3;% (
/LVW RI )LJXUHV 3DJH
Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53:
Setup and Hold Time Definition (Single- and Multi-PHY) . . . . . . . . . . . . . . . . . 158 Tristate Timing (Multi-PHY, Multiple Devices Only) . . . . . . . . . . . . . . . . . . . . . 159 Interface Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 SSRAM Interface Generic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Cell Filter Detector Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Boundary-Scan Test Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 170
Data Sheet
0-9
04.2000
3;% (
/LVW RI 7DEOHV 3DJH
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30:
OAM Functionality Determined by Layer Point Configuration . . . . . . . . . . . . . . 19 AOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Internal and external RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Cell Filter Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SCAN periods for a core clock of 51.84 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Bit Mapping for "Compressed" DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 UTOPIA polling modes. The numbers indicate the offset which is added to the PHY number. . . . . . . . 138 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Microprocessor Interface Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Microprocessor Interface Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Microprocessor DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Transmit Timing Upstream (16-Bit Data Bus, 50 MHz at Cell Interface, Single PHY) . . . . . . . . . . . . . . . . . 161 Receive Timing Upstream (16-Bit Data Bus, 50 MHz at Cell Interface, Single PHY) . . . . . . . . . . . . . . . . . 161 Transmit Timing Downstream (16-Bit Data Bus, 50 MHz at Cell Interface, Singel PHY) . . . . . . . . . . . . . . . . . 162 Receive Timing Downstream (16-Bit Data Bus, 50 MHz at Cell Interface, Single PHY) . . . . . . . . . . . . . . . . . 162 Transmit Timing Upstream (16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 163 Receive Timing Upstream (16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 164 Transmit Timing Downstream (16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 165 Receive Timing Downstream (16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 166 SSRAM Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Cell Filter Detecor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Boundary-Scan Test Interface AC Timing Characteristics . . . . . . . . . . . . . . . . 170 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Layer Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Data Sheet
0-10
04.2000
3;% (
2YHUYLHZ
2YHUYLHZ
The PXB 4340 E ATM OAM Processor is a member of the Infineon ATM622 chip set. The whole chip set consists of: * PXB 4330 E ATM Buffer Manager ABM * PXB 4340 E ATM OAM Processor AOP * PXB 4350 E ATM Layer Processor ALP * PXB 4360 F Content Addressable Memory Element CAME
Main ATM Layer functionality is achieved with only two chips, ALP and ABM. The combination of these two devices provides elementary ATM functionality like header translation, policing, OAM support, multicast and traffic management (Fig.1). The functionality is upgradeable to full OAM support by the AOP (Fig.2) and to arbitrary header translation by CAME (Fig.3).
Conn. RAM UTOPIA
Pol. RAM UTOPIA
Pointer RAM
Cell RAM UTOPIA
P H Ys
PXB 4350 E
PXB 4330 E
ALP
ABM
Conn. RAM
Cell RAM
)LJXUH
&KLSVHW FRQILJXUDWLRQ IRU PDLQ $70 OD\HU IXQFWLRQDOLW\
Data Sheet
1-11
Switch (Loop)
04.2000
3;% (
2YHUYLHZ
Conn. RAM UTOPIA
Pol. RAM UTOPIA
Conn. RAM UTOPIA
Pointer RAM
Cell RAM
PXB 4350 E
PXB 4340 E
PXB 4330 E
Switch (Loop)
PHYs
ALP
AOP
ABM
S wit ch
Conn. RAM
Conn. RAM
Cell RAM
)LJXUH
&KLSVHW FRQILJXUDWLRQ IRU PDLQ $70 OD\HU IXQFWLRQDOLW\ SOXV IXOO 2$0
Conn. RAM UTOPIA
Pol. RAM
CAME UTOPIA
Conn. RAM UTOPIA
Pointer RAM
Cell RAM
Switch (Loop)
PHYs
PXB 4350 E
PXB 4340 E
PXB 4330 E
ALP
AOP
ABM
S wit ch
Conn. RAM
Conn. RAM
Cell RAM
)LJXUH
&KLSVHW FRQILJXUDWLRQ IRU PDLQ $70 OD\HU IXQFWLRQDOLW\ SOXV IXOO 2$0 DQG DU ELWUDU\ KHDGHU WUDQVODWLRQ
1-12 04.2000
Data Sheet
3;% (
2YHUYLHZ
The ATM 622 Layer devices can be used as ....
...a full switch in: ADSL Concentrators / Multiplexers (DSLAM) Access Multiplexers Access Concentrators Multiservice switches
...Line card in: Workgroup Switches Edge Switches Core Switches
UTOPIA
UTOPIA
UTOPIA
$/3
$23
$%0
)LJXUH
0LQLVZLWFK FRQILJXUDWLRQ
Data Sheet
1-13
04.2000
3;% (
2YHUYLHZ
UTOPIA
UTOPIA
UTOPIA
$/3
$23
$%0
6ZLWFK
)LJXUH
/LQH FDUG FRQILJXUDWLRQ
Due to their most flexible scaling facilities, feature set and throughput the Infineon ATM622 layer chips are the ideal devices for almost any ATM system.
Data Sheet
1-14
04.2000
XQGHU FRQVWUXFWLRQ $70 2$0 3URFHVVRU $23 3;% (
9HUVLRQ )HDWXUHV
&026
3HUIRUPDQFH * Performance up to STM-4/OC-12 equivalent ATM layer processing * Flexibel throughput from1 .. 687 Mbit/s bi-directional * Up to 16384 connections in both directions (VPC/ VCC) * Temperature range from 0C to 70C * Multiport UTOPIA Level 2 interface in up- and downstream direction according to ATM Forum, UTOPIA Level 1 and 2 specifications [ ] * * * * * *
P-BGA-352
P-BGA-352
16-bit microprocessor interface, e.g. 386EX Cell insert/extract function 32 cell FIFO buffer at UTOPIA upstream receive interface 96 cell shared buffer for up to 24 PHYs at UTOPIA downstream transmit interface Boundary scan support according to JTAG [] Internal data stream loop at ATM and at PHY side
([WHUQDO 5$0V * Two external SSRAMs for connection related data, one for upstream and one for downstream direction, 2 x 4 Mbit for 16K connections * DMA for fast data transfer between external RAM and microprocessor * All entries parity protected 2$0 )XQFWLRQV * * * * OAM Levels and Flows (F4/F5) according to ITU-T/I.610 [] and Bellcore GR-1248 [] All OAM cell types hard-wired Generation, discard, extraction and insertion of OAM cells Programmable OAM cell types for future standardization
$,65',&& )XQFWLRQV * AIS/RDI/CC function for all connections permanently active * Automatic generation of VP/VC-AIS cells at line failures
7\SH PXB 4340 E
3DFNDJH P-BGA-352-2
Data Sheet
1-15
04.2000
3;% (
2YHUYLHZ
* Automatic generation of VC-AIS cells for all VCCs of a VPC at the endpoint including automatic backward emission of VP-RDI cells * Automatic generation of VP/VC-CC cells to detect ATM layer failures * Optional internal CC function for switch test (proprietary) * Programmable guard times and cell insertion intervals * Support of CC activation/deactivation cells /RRSEDFN * Automatic loop of cells for all connections with LB ID inversion * Programmable Port ID for on the fly comparison with Location ID or Source ID of LB cells * Insertion/extraction of LB cells via microprocessor 3HUIRUPDQFH 0RQLWRULQJ * 128 simultaneous PM generation/ evaluation processors shared for up- and downstream direction * Full HW evaluation of FM cells and generation of BR cells * Full HW support of data collection according to Bellcore GR-1248 for 128 connections * Support of PM activation/deactivation cells * Support of simultaneous PM flows of F4 and F5 level * Support of adjacent PM segments in one PXB 4340 AOP * 128 PM data collection processors shared for up- and downstream direction * Collection of the following data: - Severely errored cell blocks - Errored cells - Lost high priority cells (CLP0) - Total lost cells (CLP0+1) - Transmitted high priority cells (CLP0) - Total transmitted cells (CLP0+1) - Misinserted cells - Impaired blocks 0LFURSURFHVVRU &RQWURO * Intel 386EX microprocessor Interface * Low external processing power required 7HFKQRORJ\ * * * * 0.35 CMOS, 3.3V Plastic BGA-352 package Extended temperature range from -40C to +85C Power dissipation 2.2 W
2$0 )XQFWLRQV ZKLFK DUH QRW VXSSRUWHG * * * * * Combined Monitoring and Reporting OAM cells for performance monitoring Time stamp in Forward Monitoring OAM cells Defect type and defect location fields in AIS/RDI cells Segment AIS/RDI Simultaneous generation of end-to-end and segment FM cells
1-16 04.2000
Data Sheet
3;% (
2YHUYLHZ
/RJLF 6\PERO
8SVWUHDP &RQQHFWLRQ 5$0 ,QWHUIDFH 0 0 665$0
PDVWHU
8723,$ 7UDQVPLW ,QWHUIDFH
3;% ( $23
VODYH
8723,$ 5HFHLYH ,QWHUIDFH
8723,$ 5HFHLYH ,QWHUIDFH 8723,$ 7UDQVPLW ,QWHUIDFH 7HVW -7$* ,QWHUIDFH 0LFURSURFHVVRU ,QWHUIDFH ELW
&ORFN DQG 5HVHW ,QWHUIDFH
0 0 665$0 'RZQVWUHDP &RQQHFWLRQ 5$0 ,QWHUIDFH
)LJXUH
/RJLF 6\PERO
Data Sheet
1-17
04.2000
3;% (
2YHUYLHZ
6\VWHP ,QWHJUDWLRQ
The PXB 4340 AOP is located at the ports of a switch so that each ATM cell passes two PXB 4340 AOP devices, one at the ingress port and one at the egress port. The PXB 4340 AOP assumes that all connections are set-up bi-directional with the same Local Connection Identifier LCI in both directions. In the Infineon Technologies ATM chip set environment (VHH ILJXUHV DQG ILJXUH ) the LCI is provided by the PXB 4350 ALP and contains VPI, VCI and PHY information. The PXB 4340 AOP uses pointers to define a connection as VPC or VCC (VHH ILJXUH ); the PHY number is not evaluated. If the PXB 4340 AOP is not used together with the PXB 4350 ALP it can operate on VPI or VCI identifiers only. In these cases the OAM functionality is reduced accordingly.
(optional) (optional) (optional)
(mandatory)
Conn. RAM UTOPIA
Pol. RAM
ARC UTOPIA
Conn. RAM UTOPIA
PHYs
upstream: Address reduction Policing downstream: Header translation e.g. PXB 4350 E
PXB 4340 E
AOP
ATM switch core
ALP
Conn. RAM = connection data RAM Pol. RAM = policing data RAM ARC = address reduction circuit
Conn. RAM
(mandatory)
Conn. RAM
(mandatory)
)LJXUH
/RFDWLRQ RI 3;% ( $23 RQ D 6ZLWFK 3RUW
Data Sheet
1-18
04.2000
3;% (
2YHUYLHZ
/D\HU 3RLQW &RQFHSW
This concept is introduced to enable the automatic execution of OAM functions by the AOP. For each connection, VPC or VCC the layer point is configured at connection setup. Then the OAM functions required for this layer point are executed automatically by the AOP. There are 3 different layer points: * End point EP * Segment end point SP * Intermediate point IP End points and segment end points can be originating or terminating and can belong to a VPC or a VCC; they are referenced as e.g. VPC originating end point VP-OEP or VCC terminating segment point VC-TSP. As an example a (terminating) segment end point would ignore arriving AIS cells, as AIS cells have always the end-to-end identification. The same layer point would loop arriving forward segment LB cells. 7DEOH gives a coarse overview over the OAM functions executed by the AOP at each layer point. Monitoring functions can be enabled optionally. The details are described with the upstream and downstream external RAM entries. 7DEOH 2$0 )XQFWLRQDOLW\ 'HWHUPLQHG E\ /D\HU 3RLQW &RQILJXUDWLRQ $,6 &HOO 5', &HOO 30 /% &HOO && &HOO ,QVHUWLRQ ,QVHUWLRQ *HQHUDWH ,QVHUW *HQHUDWH )RUZDUG %DFNZDUG /RRS /RRSEDFN 7HUPLQDWH QRQ QRQ (YDOXDWH 'H LQFOXVLYH LQFOXVLYH 'H $FWLYDWH 0RQLWRULQJ 0RQLWRULQ $FWLYDWLRQ J Yes No Evaluate only Intra-Domain No Monitor LB only only Yes No Yes Yes Yes Monitor Segment Segment Segment only Cells only Cells only Cells only Yes (F4 to F5 Yes Yes Yes Yes error propagation)
)XWXUH 2$0 )XQFWLRQV

,3 63 (3
Yes
Yes
Yes
1)
via 2 programmable OAM cell filters with discard/drop/monitor/ignore options
Data Sheet
1-19
04.2000
3;% (
2YHUYLHZ
In the following scenarios examples for four layer point configurations are shown. In these figures a switch with its incoming and outgoing port is represented by the symbol shown in ILJXUH .
WUDQVPLVVLRQ OLQHV 3+V\PERO RI LQFRPLQJ SRUW ZLWK $23
V\PERO RI 6ZLWFKLQJ )DEULF
V\PERO RI RXWJRLQJ SRUW ZLWK $23
)LJXUH
6\PERO IRU 6ZLWFK ZLWK $23V
The PXB 4340 AOP can be configured according to its location in the network as shown in the following examples. Within a pure ATM network VPCs may be originated or terminated. In addition VP segments can be originated or terminated as shown in ILJXUH .
IrxA IrxA!
IU
IU
VID
IID
VID
TrtrAWQ P6HArh
@qrqAWQAP6HArh
W8
WQ
W8
WQ
W8
)LJXUH
93 /HYHO 2$0 )XQFWLRQV
As VPCs are always terminated at an ingress port and originated at an egress port, the functionality of the PXB 4340 AOP is restricted accordingly. For example it is not possible to terminate VP-AIS cells at the egress port of a switch. 7DEOH shows an overview over all possible layer points. VCCs are not originated or terminated within a pure ATM network, but only VC segments (ILJXUH ).
Data Sheet
1-20
04.2000
3;% (
2YHUYLHZ
IrxA
IrxA!
IU
IU
VID
IID
VID
TrtrAW8 P6HArh
@qrqAW8AP6HArh
W8
WQ
W8
WQ
W8
)LJXUH
9& /HYHO 2$0 )XQFWLRQV
In a heterogeneous network containing ATM and non-ATM interfaces VCC origination or termination occurs at the AAL function, as e.g. Circuit Emulation Service (CES) with AAL1 or Segmentation and Reassembly (SAR) with AAL5 as shown in ILJXUH .
IrxA
IrxA!
IU 6UH
66G
IU
IID
VID
TrtrAW8 P6HArh
@qrqAW8AP6HArh
W8
WQ
W8
WQ
W8
)LJXUH
9& (QGSRLQW LQVLGH WKH 1HWZRUN
The PXB 4340 AOP in downstream direction terminates the OAM cell stream just before the AAL device which terminates the ATM connections.
Data Sheet
1-21
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ

)XQFWLRQDO 'HVFULSWLRQ 2YHUYLHZ
The PXB 4340 AOP provides full standardized OAM functionality of the ATM layer in one device, covering the functions Fault Management (AIS, RDI, CC, LB) and Performance Monitoring (FM flow, BR flow, Data Collection). It has STM-4/OC-12 equivalent throughput in upstream and downstream direction. The AIS, RDI, CC mechanism can be applied to a range of up to 16K (=16384) connections. Performance Monitoring can be done for 128 connections simultaneously with each connection selectable from up- or downstream direction. Loopback functionality can be applied to the full range of up to 16K connections (see VHFWLRQ page 27 and VHFWLRQ page 34). Data cells are transferred via industry standard Level 2, single-port/ multi-port UTOPIA interfaces based on cell level handshake. They can be adjusted for 8-bit or 16-bit data transfer. The ATM side UTOPIA interface is operating in slave mode, the PHY side UTOPIA interface in master mode. The PHY number of a cell is transported transparently through the chip, i.e. a cell input at an UTOPIA receive interface with the PHY number P is output at the corresponding UTOPIA transmit interface with the same PHY number P. Note that the PHY number is not the UTOPIA address, but contains address and handshake line pair information (see VHFWLRQ ) Two 32 bit external SSRAM blocks are provided for OAM data storage for each connection. Their size is depending on the number of supported connections (see VHFWLRQ page 139). Chip control is performed by a standard 16-bit asynchronous microprocessor interface (e.g. for 80386EX). The microprocessor can access the external RAMs any time during operation. This is necessary for connection set up/release, data read/modify/write and configuration adjustment. The external RAM is not memory mapped into the microprocessor address range. Accesses occur via a transfer register set using transfer commands or via DMA (see VHFWLRQ page 141). All functions are supported to a great extent in HW, so that SW effort is minimized. 7KURXJKSXW
Data throughput is depending on the chip operating clock SYSCLK, which is used for the chip core and the external SSRAMs. The PXB 4340 AOP needs 32 cycles of the SYSCLK to process one ATM cell. Thus in 32 cycles 64 octets are transported through the chip for a 53 octet ATM cell, giving a penalty of 53/64. Hence the ATM cell throughput is: ATM cell throughput[Mbit/s] = SYSCLK[MHz] x 16 x 53/64 = SYSCLK[MHz] x 13.25 For a frequency of 51.84 MHz the throughput is 686.88 Mbit/s. The 51.84 MHz are easy to generate, as this is 1/3 of 155.52 MHz, the generic SDH/SONET frequency. The clock of the UTOPIA interfaces is independent of SYSCLK. It should be less or equal to the SYSCLK frequency. This is not a restriction, as the transfer time for a cell in the UTOPIA interface is only 27 clock cycles.
Data Sheet
2-22
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
&HOO +DQGOLQJ
Each cell entering the PXB 4340 AOP via the upstream/downstream receive UTOPIA interface is identified either as user cell or as OAM cell. The chip recognizes all standardized OAM cells and has two programmable comparators for possible new OAM cell types. Data stored on a connection basis in the external RAMs determines if a connection is enabled and which layer point is configured (see WDEOH for all possible configurations). Accordingly the respective function is performed. * For example a VP-AIS cell would be ignored at a VP segment endpoint. * As an other example a user cell belonging to a VPC for which end-to-end performance monitoring is enabled is counted and its checksum (BIP-16) is added to the checksum in the AOP located at the VP endpoint. In the respective OAM processing block new status information is calculated, for example alarm indication bits, BIP-16 checksums, cell counts etc. Whereas user cells are never modified and are always forwarded, OAM cells can be * generated and inserted into the cell stream in up- or downstream direction * extracted from the cell stream and discarded or dropped to the receive cell buffer of the P * forwarded with or without modification * looped back with modification. For OAM cell generation the PXB 4340 AOP uses the configuration bits of the respective connection to determine the OAM cell type. Therefore it distinguishes between F4 and F5 flow and between segment and end-to-end flow. When detecting OAM cells the PXB 4340 AOP recognizes F4 or F5 OAM cells for end-to-end or segment. According to the configuration the required actions are performed. &HOO %XIIHULQJ DQG 2$0 &HOO ,QVHUWLRQ
The PXB 4340 AOP has four cell buffers located close to the two UTOPIA interfaces in each direction (ILJXUH ): * UTOPIA upstream receive interface: 32 cells, single queue * UTOPIA upstream transmit interface: 4 cells, single queue * UTOPIA downstream receive interface: 4 cells, single queue * UTOPIA downstream transmit interface: 96 cells, shared buffer with 24 queues. The 4-cell buffers satisfy the needs of the UTOPIA slave handshake at the upstream transmit and downstream receive interface. The 32 cells wide upstream receive buffer stores incoming user cells during the insertion of OAM cells. OAM cells can be generated or looped from the opposite direction. The PXB 4340 AOP uses forced insertion for all OAM cells. Forced insertion is disabled beyond a buffer filling level which is programmable for upstream direction via register OAMTHRU (see VHFWLRQ page 90 and ILJXUH , part a). The OAM cells to be inserted are lost in this case. Also see WDEOH for illustration of the cell handling at the UTPOIA upstream receive interface. When the receive buffer filling level is lower then the threshold the OAM and user cells are processed with the shown priority.
Data Sheet
2-23
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
8723,$ SULRULW\ OLVW XSVWUHDP UHFHLYH ),)2 ILOO OHYHO UHFHLYH ),)2 ILOO WKUHVKROG OHYHO WKUHVKROG 1 BR cell from downstream 1 utopia 2 LB cell from downstream 3 FM cell from downstream 4 scan poll 5 scan OAM insertion 6 P cell insertion 7 P RAM access (RMW) 8 utopia
1)
7DEOH
GRZQVWUHDP XWRSLD WUDQVPLW ),)2 QRW XWRSLD WUDQVPLW IXOO ),)2 IXOO 1 FM cell insertion backpressure to adjacent device 2 BR cell from upstream 3 LB cell from upstream 4 scan poll 5 scan OAM insertion 6 P cell insertion 7 P RAM access (RMW) 8 utopia
1 = highest priority, 8 = lowest priority
XSVWUHDP GLUHFWLRQ WR VZLWFKLQJ QHWZRUN
rApryy
8WRSLD 0DVWHU ,QWHUIDFH
"!pryyAissr sAihpxrr
sprqAvrv sAP6HApryy #pryyAissrAs VUPQD6Auhquhxr

(%pryyAuhrqAissr sApryyAqryvyrvt
2$0 3URFHVVRUV
P6HApryy rApryy
#pryyAissrAs
3,QWHUIDFH
VUPQD6Auhquhxr
GRZQVWUHDP GLUHFWLRQ WR 3+<
)LJXUH
&HOO %XIIHUV LQ 3;% $23
The downstream transmit buffer also does forced OAM cell insertion by back-pressuring user cells to the downstream receive interface and possibly to the previous chip. It is realized as shared buffer of up to 24 queues, associated to the respective PHYs. The back-pressured user cells are released in bursts of up to 687 Mbit/s when no other cells with higher priority according to WDEOH are present. These bursts must be stored by the downstream transmit buffer and released to the PHYs according to their respective speed.
Data Sheet
2-24
8WRSLD 6ODYH ,QWHUIDFH
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
The downstream transmit buffer has 2 thresholds for each queue: * the UTOPIA backpressure threshold: beyond this threshold the backpressure signal is given to the downstream receive interface for this PHY (see VHFWLRQ page 91) * the OAM cell insertion threshold: beyond this threshold the insertion of OAM cells is disabled (see VHFWLRQ page 91). As with the upstream receive buffer in this state OAM cells to be inserted are lost. The two thresholds are identical for all queues. The UTOPIA backpressure threshold should be programmed to a value lower than the OAM cell insertion threshold, this difference guarantees a cell storage space for OAM cells (see ILJXUH , part b).
cell buffer
cell buffer
pryyAvrvAuruyq qrhAP6HUCS9

8ryyAvrvAuruyq rhAP6HUCSV
OAM cells
if a queue exceeds this threshold : no more OAM cells are inserted
ihpxrrAuruyq qrhA7QUCS9
user cells

rrAvAr
user cells
if a queue exceeds this threshold : no more OAM cells are inserted. They are lost.
if a queue exceeds this threshold : no more user cells are accepted
rrAvAr
hArhArprvrAADAP
iAqrhAhvAADAP
)LJXUH
7KUHVKROGV LQ 8723,$ FHOO EXIIHUV
The ATM cell load should be selected by the user in a way that the probability to loosing OAM cells is almost zero (e.g. 10-11). This is done by reserving bandwidth for the inserted OAM cells. OAM cell bandwidth is mainly depending on the selected PM block size (128, 256, 512, 1024). In worst case, when F4 and F5 level PM cell streams are generated, the overhead is still less than 2%. Lost OAM cells do not lead to system malfunction. If e.g. an FM cell is lost the PM processor continues to count user cells and BIP-16 checksums. The correct values will be sent out with the next block. Thus block size would be e.g. 256 instead of 128 in case of a lost cell. The insertion of AIS/RDI/CC cells will only be halted temporarily during the (very unlikely) case of a buffer overflow. An LB cell to be looped, however, will be lost. Here only the repeat function would help.
Data Sheet
2-25
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
$GGUHVVLQJ RI H[WHUQDO 5$0V
The external RAMs for the storage of connection related OAM data are symmetrical in up- and downstream direction. Also the addressing is symmetrical as the LCI values for forward and backward connection are identical. Note that according to the standards each ATM connection is set-up bi-directional, but not necessarily with the same bit rate in both directions. Both external RAMs are divided into an F4 and an F5 OAM table. Each connection entry has 4 dwords. With the LCI of the cell first the VC-specific table is addressed. Therein an F4 pointer is contained pointing to a VP-specific entry. There are two cases, both depicted in the circle of ILJXUH .
.
16383 16382 16381 :
LCI (VCCa)
F5 entry
16383 16382 16381 :
:
F4 entry
Connections:
LCI (VCCb)

F5 entry
F4 pointer: LCI2(VPCt)
LCI (VPCi)
VPCt VCCa VCCb

don't care
F4 pointer: LCI2=LCI : 2 1 0
: : : : :
F4 entry : :
VPCi
: 2 1 0

F5 OAM table
)LJXUH 1. 3RLQWHU 6WUXFWXUH RI XS DQG GRZQVWUHDP 2$0 7DEOHV
F4 OAM table
2.
A VPC intermediate point In this case the F5 entry is "don't care", except some common fields. See e.g. VPCi in ILJXUH . The VP-specific entry contains the OAM data for the VPC. A terminated VPC decomposed into VCCs In this case each VCC has an F5 entry with identical F4 pointers pointing all to the same F4 entry. See e.g. VCCa and VCCb of VPCt in ILJXUH .
Data Sheet
2-26
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
2$0 )XQFWLRQV 2YHUYLHZ
There are two groups of applications for OAM functions: alarms and measurements. Alarm functions inform users and network operators about network failures. These include the OAM functions * Alarm Indication Signal (AIS) * Remote Defect Indication (RDI) * Continuity Check (CC). AIS and RDI are used to convey transmission line failure information to subscriber and network operator; CC detects ATM layer failures. As failure events are unpredictable the alarm supervising HW is always running. When a failure occurs the notification process starts automatically. Measurements are initiated for diagnosis purposes by the network operator. Therefore these functions do not need to be active permanently for all connections. The respective OAM functions are: * Loopback LB * Performance Monitoring PM LB checks the connectivity of a connection by sending a single cell which is looped back at predefined points. LB is used e.g. immediately after connection set-up or periodically to check all permanent connections of a network using end-to-end or segment LB. A network operator could also use intra-domain LB to localize a failed link. Another option for loopback are subscriber initiated loops either end-to-end to the partner or access line LB to the first node in the network. PM is a more precise tool than LB. It checks not only the connectivity, but the real performance of a connection in terms of bit failures and cell losses. As it requires complex HW support and SW performance PM will not be activated permanently for all connections. E.g. VPCs or permanent VCCs could be monitored if a subscriber pays for this service. Also a network operator would use PM to check the quality of a connection if a subscriber complains about it. $ODUP 2$0 )XQFWLRQV $,65',&&
There are two types of failures detected by the alarm functions: transmission line failures and ATM layer failures. Transmission line failures are e.g. line brakes, failures of lasers or failures of reception diodes. Typical ATM layer failures are the misrouting of cells in the switching fabric or a falsified entry in a routing table. In this case all cells of a connection are forwarded to a wrong destination. 7UDQVPLVVLRQ /LQH )DLOXUHV $,65', Transmission line failures are recognized by the receiving PHY and conveyed to the PXB 4340 AOP by the on-board control processor. It is sufficient to set one single bit for the respective PHY to initiate the periodic insertion of AIS cells for all affected connections. In the external RAM entry a bit CARIEN exists for F5-AIS and a bit PARIEN for F4-AIS ( for CARIEN see VHFWLRQ page 100, for upstream and VHFWLRQ page 112, for downstream; for PARIEN see VHFWLRQ page 107, for upstream and VHFWLRQ page 118, for downstream). When these bits are set to '1', the insertion of AIS cells is enabled. Note, that no F4 OAM/User-Flow is supported if the LCI-Mode "10" in register UTCONF1 is selected (see VHFWLRQ page 88). Further the bit DISF4 and DISF5 in the external RAM entries have to be set to '0' to enable the
Data Sheet 2-27 04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
F4/F5 processing (see VHFWLRQ page 98, VHFWLRQ page 110, for DISF5 in upand downstream direction; VHFWLRQ page 105, VHFWLRQ page 116, for DISF4 in up- and downstream direction). Otherwise all F4/F5 cells are discarded at the receiving point. The PXB 4340 AOP automatically inserts VP-AIS cells for VPCs and VC-AIS cells for VCCs. )LJXUH shows that this case occurs at the incoming port of a switch.
/LQH &DUG 3RUW D AOP
6ZLWFK )DEULF 3RUW E
6DTApryy
yvrAshvy vqvphv
rAQC r
3RUW F
6DTApryy
3
)LJXUH
([DPSOH IRU /LQH )DLOXUH 1RWLILFDWLRQ YLD $,6 FHOOV
The generated VC-AIS cells travel up to the endpoint of the connection, which normally is the user terminal. Thus within a very short time delay - determined by the control processor's response time, the PXB 4340 AOP insertion delay and the cell transfer time - the user is informed about the failure. The generated VP-AIS cells travel up to the VP terminating endpoint which normally is within the network. At the VP terminating endpoint - which is always at the incoming port of a switch - VCAIS cells must be generated for all VCCs contained in the VPC. Again, all affected user terminals are informed. The PXB 4340 AOP automatically performs the following actions when receiving VP-AIS cells at a VP terminating endpoint (see ILJXUH ):
Data Sheet
2-28
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
configured as an F4 originating end point
configured as an F4 intermediate point
configured as an F4 terminating end point
configured as an F5 terminating end point end of the OAM flow
F5 F4 AIS cell F5 1 3
F5 AIS cell F5 AIS cell
4 F5 RDI cell F5 RDI cell AOPE configured as an F4 terminating end point AOPE configured as an F4 intermediate point
F4 RDI cell
2
AOPE configured as an F4 originating end point
AOPE configured as an F5 originating end point begin of the OAM flow
for all VCCs in one VPC: F5 AIS cells are sent
line broken
discard F4 AIS cell
discard F4 RDI cell
)LJXUH
93$,65',)ORZ )$,65',)ORZ
* Discard of VP-AIS cells (see ILJXUH , marker ) * Execution of the (VP-)AIS state diagram shown in ILJXUH for the respective VPC. * Insertion of VP-RDI cells in backward direction. This informs the originating endpoint of the VPC about the failure. RDI makes sense in cases where the failure of the line affects only one direction. The automatic RDI generation in backward direction assumes bi-directional connections with the same identifier (LCI) in both directions (see ILJXUH , marker o). * Insertion of VC-AIS cells in forward direction for each VCC of this VPC. This informs all users sharing this VPC about the failure in the network (see ILJXUH , marker i). * Declaration of AIS/RDI IDLOXUH states after 3.5 seconds (standard) persistence of AIS defect state. The cell insertions continue unaffected. At the originating endpoint of the VPC the following actions are perfomed: * Discard of VP-RDI cells (see ILJXUH , marker o) * Execution of the RDI state diagram shown in ILJXUH . * Declaration of RDI failure state after 3.5 seconds (standard) duration of RDI defect state. The AIS state diagram executed at the sink endpoint of a connection is shown in ILJXUH . Note that in accordance for the anomaly-defect-failure mechanism only transitions to and from failure state are notified to the microprocessor. This avoids unnecessary interrupts.
Data Sheet
2-29
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
Setup of a new connection
One valid user cell or one CC cell if Terminating CC is disabled and no AIS cell is received for a certain time (programmable <= 3,5 sec, default 2,5 sec)
Normal Operation
First AIS cell detected One valid user cell or one CC cell or if Terminating CC is disabled: no AIS cell is received for a certain time (programmable <= 3,5 sec, default 2,5 sec) notification to uP
AIS-Defect
Transmit periodically (1 cell/s) AIS cells respectively RDI cells. First AIS cell within 0.5 s.
Receiving of AIS cell for a certain time (programmable <= 7,5 sec, default 3.5 sec) notification to uP
AIS-Failure
Transmit periodically (1 cell/s) AIS cells respectively RDI cells.
)LJXUH
$,6 6WDWH 'LDJUDP
setup of new connection
No RDI cell received for a certain time (programmable <= 3,5 sec, default 2,5 sec)
Normal Operation
First RDI cell detected
RDI-Defect
No RDI cell received for a certain time (programmable <= 3,5 sec, default 2,5 sec)
Receiving RDI cells for a certain time (programmable <= 7,5 sec, default 3,5 sec)
notification to uP
notification to uP
RDI-Failure
)LJXUH
5', 6WDWH 'LDJUDP
Data Sheet
2-30
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
The actual F5-AIS/RDI state is indicated by bits 14..19 in Dword2 of the downstream external Ram entry (VHFWLRQ page 114) and the upstream external RAM entry (VHFWLRQ page 102). For the actual F4-AIS/RDI state information use bits 22..27 in Dword4 of the downstream external RAM entry (VHFWLRQ page 116) and the upstream external RAM entry (VHFWLRQ page 105). The P is informed by the interrupts DCSTTR for downstream F5, UCSTTR for upstream F5, DPSTTR for downstream F4 and UPSTTR for upstream F4 state transitions (VHFWLRQ page 83). Both forward and backward cell insertions are initiated by the SCAN mechanism (see VHFWLRQ ). All delay times given are default values, recommended by []. The PXB 4340 AOP allows to program these values in multiples of the 0.5 second SCAN period given by the microprocessor. Therefore consider the register description of SCCONF1 (see VHFWLRQ page 79). The 0.5 second SCAN period determines the insertion delay for OAM cells. If the SCAN mechanism has passed a connection entry just before an AIS condition became true the maximum waiting time for the next SCAN access is about 0.5 second. $70 /D\HU )DLOXUHV && The mechanism to detect failures like misrouting is the Continuity Check (CC). Its idea is to insert dummy cells in a connection if it is inactive, i.e. if the user is not sending data cells. The dummy cells are called CC OAM cells and are inserted at the originating end/segment point of a connection after a one second absence of user cells. The repetition interval is also one second. At the connection/segment endpoint the CC cells are discarded. If no user or OAM cells are received within 3.5 seconds the Loss of Continuity (LOC) defect state is declared. Like AIS state LOC causes the automatic insertion of VP-AIS or VC-AIS cells for the affected connections. If LOC is detected at a terminating endpoint RDI cells are generated in backward direction. )LJXUH shows an example for the operation of CC: two VCCs entering a switch at ports a and b should both be forwarded to port c. Due to misrouting within the switching fabric the cells of VCC b are forwarded to an unconnected switch output, where they are lost without being notified. The CC detection function at port c, however, detects the absence of user cells after the 3.5 seconds time-out and inserts VC-AIS cells for connection b. The time values given are values recommended in [6]. The PXB 4340 AOP allows to progam them in a wide range. The PXB 4340 AOP supports the CC function for all 16384 connections in both up- and downstream direction. Setting one bit in the respective connection RAM is sufficient to activate the origination or the termination of a CC flow. This is bit 11 in Dword1 (up-/downstream) for originating F5 segment CC, bit 10 in Dword1 (up-/downstream) for originating F5 end-to-end CC and bit 11 in Dword4 (up-/downstream) for originating F4 segment CC (see VHFWLRQ page 98). All other actions are automatic: At the CC origination point (see ILJXUH and ILJXUH ): * continuous supervision of user cell stream (see ILJXUH , marker ) * periodic insertion of CC cells in one second intervals after one second (standard) time-out (see ILJXUH , marker )
Data Sheet
2-31
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
Switch Fabric misrouting Port b
VCCb
Port c AOP
VC-AIS(b) VCCa
Port a
VCCa
timeout 3.5 s
user cells & VC-CC cells of VCCb
)LJXUH
([DPSOH IRU 0LVURXWLQJ )DLOXUH 'HWHFWLRQ
configured as an F4 intermediate point and originating segment point configured as an F4 intermediate point and terminating segment point configured as an F5 terminating end point end of the OAM flow
configured as an F4 terminating end point
F4 user cells
1
F4 segment CC
3 timeout (no user or cc cells)
F5 AIS cell F4 AIS cell F5 AIS cell
2
F4 segment CC
1
F4 RDI cell F5 RDI cell F5 RDI cell AOPE configured as an F4 intermediate point and terminating segment point AOPE configured as an F4 intermediate point and originating segment point AOPE configured as an F4 originating end point AOPE configured as an F5 originating end point begin of the OAM flow
for all VCCs in one VPC: F5 AIS cells are sent
connection broken
discard received CC cells
)LJXUH
) VHJPHQW && )ORZ
Data Sheet
2-32
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
setup of new connection CC activated for VPC/VCC by uP
Insert CC cell if no user cell transmitted for programmable Ts (<= 1.5 sec, default 1 sec)
CC inactive
CC deactivated for VPC/VCC by uP
CC active
)LJXUH
&RQWLQXLW\ &KHFN &HOO *HQHUDWLRQ 6WDWH 'LDJUDP
At the CC termination point (see ILJXUH ): * discard of CC cells (see ILJXUH , marker o) * declaration of LOC GHIHFW state and insertion of AIS cells in one second intervals after 3.5 seconds absence of user or OAM cells (see ILJXUH , marker i) * declaration of LOC IDLOXUH state if LOC defect state persists for 2.5 seconds.
setup of new connetion CC activated for VPC/VCC by uP First valid ATM cell for VPC/VCC received Send periodically AIS/RDI every 1 second
CC inactive
CC deactivated for VPC/VCC by uP
CC active
No valid ATM cell for VPC/VCC received for programmable Tr (<= 7.5 sec, default: 3.5 sec) First valid ATM cell for VPC/VCC received
Loss of Continuity Defect
No valid ATM cell for VPC/VCC received for programmable Tdef (<= 7.5 sec, default: 2.5 sec)
notification to uP
notification to uP
Loss of Continuity Failure
Send periodically AIS/RDI every 1 second
)LJXUH
&RQWLQXLW\ &KHFN (YDOXDWLRQ 6WDWH 'LDJUDP
The LOC failure state is notified to the control processor, while still AIS cells are automatically generated. This additional filtering according to the standards avoids frequent notifications to the microprocessor due to sporadic errors (see bits 3..0 of register ISR0, VHFWLRQ ). All cell insertions are initiated by the SCAN mechanism (see VHFWLRQ ). The delay times given are default values, recommended by I.610 []. The PXB 4340 AOP allows to program these values in multiples of the SCAN frequency which in turn is given by the microprocessor. The corresponding register is named SCCONF0 (see VHFWLRQ page 78).
Data Sheet
2-33
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
To further limit the load for the microprocessor the DMA function is provided which transfers relevant status bits for all connections to the control processor memory in the background (see FKDSWHU ). The insertion of AIS cells occurs as in the AIS state (FKDSWHU ), i.e. with periodic insertion of VP-AIS or VC-AIS cells and VP-RDI cells in backward direction. No additional AIS cells are inserted if AIS and LOC state are declared simultaneously. Additionally to the standardized CC an Internal Continuity Check ICC is provided as proprietary function. It uses CC cells with a specially marked header (see VHFWLRQ ) between incoming and outgoing port. If no AOPE Continuity Check is active a network element ICC can be activated in order to check the connectivity across the switching network between AOPE upstream and AOPE downstream. The functionality of ICC does not differ from the AOPE CC since a received ICC cell is treated like a CC cell, i.e. the same checkers/generators which otherwise do CC processing are used for ICC with the following consequences : * insertion of ICC cells in the upstream direction of the AOPE (originating point) if no valid user cell has been received for a specified time interval of one second. * supervision of arrived user cells or ICC cells at downstream direction of the AOPE (terminating point) within a specific time interval of 3.5 +/- 0.5 seconds. * Loss of ICC cells in downstream direction of the AOPE will result in AIS/RDI generation as described in VHFWLRQ . The AIS/RDI generation is adjustable via VPC/VCC. ICC can be activated by software for each valid VPC/VCC. ICC cells are distinguished from CC cells by the HK bits (HK=100) in the UTOPIA cell header (UDF1 field). For ICC segment CC cell format is used. If evaluation of the UDF1 field is not enabled, ICC is not supported. For ICC the VP/VC segment configuration flags are not relevant. Therefore 3 ATM layer configuration cases for upstream cell generation are remaining : * generation of VP ICC cells at VP intermediate points * geneartion of VC ICC cells at VC originating end points * generation of VC ICC cells at VC intermediate points For downstream evaluation are remaining : * evaluation of VP ICC cells at VP intermediate points * evaluation of VC ICC cells at VC terminating end points * evaluation of VC ICC cells at VC intermediate points ICC cells never leave a switch while ICC is intended for connection supervision within a switch. 1HWZRUN &RQQHFWLYLW\ &KHFN /%
*HQHUDO The loopback (LB) OAM function is intended for checking the connectivity of a virtual connection by sending a single LB cell along the connection. The LB cell is extracted at well defined points of the network and sent back to the source via the backward connection. Note that each ATM connection has an associated connection in backward direction with the same connection identifiers.
Data Sheet
2-34
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
There are three possibilities for specifying the loopback point of an LB cell: * End-to-end LB processing * Segment LB processing * End Point LB processing The loopback function determines which loopback activities are executed dependent on ATM layer configuration of the network element (originating segment/end point, terminating segment/ end point, intermediate point) and the received F4/F5 LB cell at the AOPE (upstream, downstream). Loop of LB cells including reset of the LB indication bit in the cell is done without microprocessor interaction at the respective segment or connection end points. The VPC consistency flag (see VHFWLRQ page 39) indicates the availability of the VPC to the microprocessor at the loopback port. The loopback processing selects the loopback actions dependent on the loopback state and the loopback location/source ID flag of the F4/F5 flow and the content of the received F4/F5 LB cell payload (LB indication, LB location ID, LB source ID) at the AOPE (upstream or downstream). The evaluation of the LB location/source ID of the LB cell payload is switchable via the LB location/source ID flag. The correlation tag of the LB cell payload is supported by SW. If the connection is in loopback state (LB state = 1) then an LB cell can be copied or dropped from cellstream into the cell buffer of the P. If the LB location/source ID flag is set a compare has to be done between the LB location/source ID and the network element ID (see VHFWLRQ page 98). At the originating segment/end point, the F4/F5-LB cell can be inserted into the cellstream in upstream or downstream direction. The insertion of the LB cell is done by SW via the transmit cell buffer of the P (see marker in ILJXUH , ILJXUH and ILJXUH ). If a looped F4/F5 LB cell arrived at the originating segment/end point, this cell is dropped to the cell receive buffer of the P (see marker o in ILJXUH , ILJXUH and ILJXUH ). Cell insertion and extraction functions are described in VHFWLRQ page 49. The ATM layer configuration, the loopback state of a connection and the LB location/source ID flag are VP and VC connection specific data. This data is located in external RAMs for upstream and downstream direction (see VHFWLRQ page 98). Note that the automatic loop function assumes identical connection identifiers for both forward and backward connections.
)) (QGWR(QG /RRSEDFN 3URFHVVLQJ If the LB indication bit of an LB cell is equal to 1 the LB cell is forwarded to the terminating end point. At the terminating end point the LB indication flag is set to 0 and the LB cell is looped back (loopback point, see ILJXUH , marker o). If the LB indication is equal to 0 (LB cell already looped) and the connection is in LB state (LB state = 1) and the LB source ID of the LB cell is equal the network element ID (LB source ID match) then the LB cell is copied to the receive cell buffer of the P and the LB cell is also forwarded to the terminating end point (see ILJXUH , marker i). If the LB source ID flag of this connection is disabled the same loopback actions are done. If the connection isn't in LB state (LB state = 0) or an LB source ID mismatch occurs the LB cell is forwarded to the terminating end point (see ILJXUH , marker ).
Data Sheet 2-35 04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
configured as an F5 orginating end point
configured as an F4 originating end point and F5 originating segment point
configured as an F4 intermediate point
configured as an F4 intermediate point
configured as an F4 terminating end point and F5 intermediate point
configured as an F5 terminating segment and F5 terminating end point
2 1 set LB indication flag to 0
LB cell looped back 4 3 5
AOPE
AOPE
LB status = 1
AOPE
LB status = 1
AOPE
LB status = 0
AOPE
configured as an F4 originating end point and F5 intermediate point
AOPE
configured as an F5 originating segment and F5 originating end point
configured as an F5 terminating end point
configured as an F4 terminating end point and F5 terminating segment point
configured as an F4 intermediate point
configured as an F4 intermediate point
insertion of F4 LB cell
drop LB cell to P receive cell buffer
copy LB cell to P receive cell buffer when LB status and LB source ID match and LB cell is allready looped
set LB indication flag to 0
)LJXUH
([DPSOH RI ) (QGWR(QG /RRSEDFN 3URFHVVLQJ
7DEOH (QGWR(QG /RRSEDFN 3URFHVVLQJ /% /% VWDWH /% /RFDWLRQ /% /RFDWLRQ /RRSEDFN $FWLRQ LQGLFDWLRQ 6RXUFH ,' )ODJ 6RXUFH ,' 1 don't care don't care don't care forward LB cell to terminating end point 0 0 don't care don't care forward LB cell to terminating end point 1 disabled don't care * copy of LB cell to P receive cell buffer enabled match * forward LB cell to terminating end point enabled mismatch forward LB cell to terminating end point
)) 6HJPHQW /RRSEDFN 3URFHVVLQJ If the LB indication bit of an LB cell is equal to 1 and an LB location ID of the LB cell is equal to the network element ID (LB location ID match) the loopback indication flag is set to 0 and the LB cell is looped back (loopback point, see ILJXUH , marker o). Additionally the unchanged LB cell is forwarded to the terminating segment point. This cell is looped back at the terminating segment point (see ILJXUH , marker i). If the LB location ID flag is disabled or an LB location ID mismatch occurs the LB cell is forwarded to the terminating segment point (see ILJXUH , marker u )
Data Sheet 2-36 04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
.
configured as an F5 orginating end point configured as an F4 originating end point and F5 originating segment point configured as an F4 intermediate point configured as an F4 intermediate point configured as an F4 terminating end point and F5 intermediate point configured as an F5 terminating segment and F5 terminating end point
set LB indication flag to 0 1 F5 Segment LB LB cell looped back 3 LB cell looped back 4 2
4
5
AOPE
AOPE
LB status = 1
AOPE
LB status = 1
AOPE
LB status = 0
AOPE
LB status = 0
AOPE
configured as an F5 originating segment and F5 originating end point
configured as an F5 terminating end point
configured as an F4 terminating end point and F5 terminating segment point
configured as an F4 intermediate point
configured as an F4 intermediate point
configured as an F4 originating end point and F5 intermediate point
insertion of F5 LB cell
drop LB cell to P receive cell buffer
set LB indication flag to 0
)LJXUH
([DPSOH RI ) 6HJPHQW /RRSEDFN 3URFHVVLQJ
If the LB indication of an LB cell is equal to 0 (LB cell already looped) and the connection is in LB state (LB state = 1) and the LB source ID of the LB cell is equal to the network element ID (LB source ID match) the LB cell is copied into the receive cell buffer of the P and the LB cell is forwarded to the terminating segment point. If the LB source ID flag of a connection is disabled the LB cell is also copied into the receive cell buffer of the P and the LB cell is forwarded to the terminating segment point. 7DEOH 6HJPHQW /RRSEDFN 3URFHVVLQJ /% /% 6WDWH /% /RFDWLRQ /% /RFDWLRQ /RRSEDFN $FWLRQ ,QGLFDWLRQ 6RXUFH ,' )ODJ 6RXUFH ,' 1 don't care enabled match * set LB indication to 0 * LB cell is looped back * forward of LB cell to terminating segment point enabled mismatch forward of LB cell to terminating segment point disabled don't care 0 0 don't care don't care forward of LB cell to terminating segment point 1 disabled don't care * copy of LB cell to P receive cell buffer enabled match * forward of LB cell to terminating segment point enabled mismatch forward of LB cell to terminating segment point
Data Sheet
2-37
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
)) (QG 3RLQW /RRSEDFN 3URFHVVLQJ If the LB indication of an LB cell is equal to 1 and an LB location ID of the LB cell is equal to the network element ID (LB location ID match) the LB indication flag is set to 0 and the LB cell is looped back (loopback point, see ILJXUH , marker o). This means that the AOPE ASIC sends the LB cell to the opposite direction of AOPE (from upstream direction to downstream direction and in opposite direction). In case of an LB location ID mismatch the LB cell is discarded. Additionally the loopback processing sets a 'consistency' flag for the P only at the VP terminating end point (AOPE upstream) in order to support the VPCI consistency check. The 'consistency' flag is reset by SW. If the LB indication of an LB cell is equal to 0 (LB cell already looped) and the connection is in LB state (LB state = 1) and the source ID of the LB cell is equal the network element ID (LB source ID match) the LB cell is dropped into the receive cell buffer of the P (see ILJXUH , marker i). If the LB source ID flag of a connection is disabled or an LB source ID mismatch occurs then the LB cell is discarded. If the connection isn't in LB state (LB state = 0) the LB cell is discarded.
configured as an F4 originating end point and F5 originating segment point configured as an F4 terminating end point and F5 intermediate point configured as an F5 terminating segment and F5 terminating end point
configured as an F5 orginating end point
configured as an F4 intermediate point
configured as an F4 intermediate point
1
2 VPCI consistency flag
3
LB cell looped back
AOPE
AOPE
LB status = 1
AOPE
LB status = 1
AOPE
LB status = 0
AOPE
configured as an F4 originating end point and F5 intermediate point
AOPE
configured as an F5 originating segment and F5 originating end point
configured as an F5 terminating end point
configured as an F4 terminating end point and F5 terminating segment point
configured as an F4 intermediate point
configured as an F4 intermediate point
insertion of F4 LB cell
drop LB cell to P receive cell buffer
set flag for VPCI consistency check
)LJXUH
([DPSOH RI ) (QG 3RLQW /RRSEDFN 3URFHVVLQJ
Data Sheet
2-38
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
7DEOH (QG 3RLQW /RRSEDFN 3URFHVVLQJ /% /% VWDWH /% /RFDWLRQ /% /RFDWLRQ /RRSEDFN $FWLRQ LQGLFDWLRQ 6RXUFH ,' )ODJ 6RXUFH ,' 1 don't care don't care match * set LB indication flag to 0 * LB cell looped back * set a flag for VPCI consistency check mismatch discard LB cell 0 0 don't care don't care discard LB cell 1 disable don't care drop of LB cell to receive cell buffer of the P enabled match enable mismatch discard LB cell
93&, &RQVLVWHQF\ &KHFN VPCI consistency check is supported by the LB function at the VPC terminating end point. The loopback function of AOPE (upstream) indicates 'VPCI consistency' by setting a flag, if an F4 end-to-end LB cell is received and successfully looped back at VPC terminating end point. This flag is reset by SW. The bit VPCCHK in Dword4 of the external RAM entry is the corresponding to this flag (see VHFWLRQ page 105, and VHFWLRQ page 116).
&RQQHFWLRQ 4XDOLW\ 0HDVXUHPHQW 30
*HQHUDO To make measurement of connection quality possible, the AOPE provides a number of counters. The Performance Monitoring (PM) flow allows the use and evaluation of these counters. The counter values are stored in the internal PM main RAM (see VHFWLRQ page 121). The AOPE can process 128 bidirectional PM flows configurable for the upstream or downstream direction on a connection basis (see VHFWLRQ page 98). PM flows can be applied to the F4/ F5 layer as a segment flow or end-to-end flow. In the PM flow, forward error detection information (e.g. the error detection code) is communicated by the PM end points using Forward Monitoring (FM) cells. The performance monitoring results are received on the reverse direction using Backward Reporting (BR) cells. After a block of user cells has been received, the related FM cell can be inserted directly within the next cell cycle. The blocksize is defined in VHFWLRQ page 122. The first FM cell sent from the PM originating point is used to initialize the PM terminating point. After an FM cell has been received at a PM terminating point, the corresponding BR cell is generated (if enabled) and sent back via the opposite direction, i.e. if it is received upstream it is sent downstream and if it is received downstream it is sent upstream.
Data Sheet 2-39 04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
The first BR cell is generated when the first FM cell for this PM flow has been received. This BR cell carries valid data to initialize the BR data collection point, but no valid data for data collection. Only the following BR cells contain valid data for data collection. The PM function is split into three different parts: * PM generation * PM analysis and loop * PM data collection. PM generation includes * Calculation of total user cell count for all cells and for high priority cells (CLP=0) * Calculation of a BIP-16 checksum over user cell payload * Generation of FM cells containing the calculated results. The FM cells are coded as F4 or F5 automatically for VPCs and VCCs, respectively, end-end or segment as specified. FM cell sequence number and CRC-10 checksum are also generated. The blocksize can be selected between 2 and 65536. The optional time stamp of the FM cell is not generated. Forced OAM cell insertion is used for both up- and downstream FM cell insertion. During insertion of FM cells the user cell stream is stored in the respective buffers (see VHFWLRQ ). PM analysis and loop include * Calculation of total user cell count for all cells and for high priority cells (CLP=0) * Extraction of FM cells * Appending of calculation results to the end of the cell * Conversion of the cell into a BR cell * Re-insertion of the BR cell in opposite direction. PM analysis uses the same PM processor circuits as the generation process. In total 128 PM processor circuits are shared by up- and downstream direction. For PM data collection 128 circuits are provided, which are independent of the PM processor circuits. Both PM and data collection processors have their respective entries in the internal PM/ data collection RAMs. The assignment of PM and data collection processors to connections in up- or downstream direction is arbitrary. VPCs and VCCs can be assigned by programming pointers in the F4 and F5 entries, respectively (see VHFWLRQ page 121, and VHFWLRQ page 123). ([DPSOH A typical PM scenario is shown in ILJXUH in case of VP end-to-end monitoring. Two nodes are involved, Node 'a' where the VPCa-b is created and Node 'b' where VPCa-b is terminated. In backward direction the associated VPCb-a is created in Node 'b' and terminated in Node 'a'. Creation of a VPC allways occurs at an outgoing port of a node and termination at an incoming port. Hence the Originating End Point (OEP) of VPCa-b is located in the downstream part of the PXB 4340 AOP in Node a, and the Terminating End Point (TEP) of VPCa-b is located in the upstream part of the PXB 4340 AOP in Node b. For VPCb-a the situation is mirrored according to ILJXUH .
Data Sheet
2-40
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
1RGH D
AOP
r
1RGH E
VPC TEP
VPC OEP
AOP
WQAH
WQAH pryy
r pryy
SWITCH
QHApr trrhrAAqr
QHApr hhyrAAqr
WQ7S pryy WQ7S pryy WQ7S pryy
QHAqhh pyyrpv
QHAqhh pyyrpv
WQ8AU@Q vppr
WQ8AP@Q vppr
A WQ8hi A WQ8ih
)LJXUH
30 &RQILJXUDWLRQ ([DPSOH
Note that between Nodes 'a' and 'b' a number of intermediate nodes can be located. All PXB 4340 AOP chips on these nodes must be configured either as Originating or Terminating Segment Points (OSP, TSP) or as Intermediate Points (IP). One of the 128 PM processors in the PXB 4340 AOP upstream part of Node a is configured in generate mode, i.e. it monitors all user cells of VPCa-b, computes PM data and inserts it after blocks of user cells into the cell stream as Forward Monitoring (FM) cells. At the terminating PXB 4340 AOP one of the 128 PM processors is configured in analyze mode, i.e. it monitors all user cells of VPCa-b, computes PM data and adds it to the PM data contained in the FM cells. The FM cells are extracted from the cell stream, converted into Backward Reporting (BR) cells and re-inserted in backward direction in VPCb-a. The conversion into BR cells includes the calculation of the differences between measured PM data and the PM data contained in the FM cells. The differences are written into the BR cells. Back at the originating Node a, the BR cells are discarded after evaluation. Note that the re-insertion of BR cells in backward direction assumes the same identifier (LCI) of the backward direction connection.
Data Sheet
2-41
SWITCH
pryy
pryy
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
30 'DWD &ROOHFWLRQ The data collection procedure is independent of the FM/BR cell mechanism. It uses one of the 128 data collection processors contained in the PXB 4340 AOP. Each of them can evaluate the BR data flow from upstream or downstream direction. Data collection can be done at any node along the way of the BR cells. In the example of ILJXUH Nodes a or b could be selected for data collection. It can be done concerning the data of an incoming BR cell or after a BLER0+1 calculation concerning the data of an incoming FM cell. The TUCdiff/TUCdiff0 calculation has to be done before the Data Collection can be started. In the Data Collection processing it is first proved whether TUCdiff/TUCdiff0 is zero. If it is zero, the BLER0+1 is checked. If TUCdiff/ TUCdiff0 is not zero, it is not reasonable to prove the BLER0+1. According to the defined thresholds certain counters have to be updated. 7DEOH is a summery of counters, which are updated for Data Collection (see VHFWLRQ page 123). 7DEOH 8SGDWHG FRXQWHUV IRU 'DWD &ROOHFWLRQ $FURQ\PV WHUP IMPB impaired blocks SECB severely errored cell blocks SECBERR severely errored cell block errored counter ERRC errored cells LOSTC lost cells MISC misinserted cells TLOST0 total lost cells SECBMIS severely errored cell blocks of misinserted cells LOSTC0 lost cells of the CLP=0 flow TLOSTC0 total lost cells of the CLP=0 flow TRANSUC0 transmitted user cells of CLP=0 flow TRANSUC transmitted user cells of CLP-0+1 flow The Counters SECB, SECBERR, SECBMIS and TLOSTC0 are updated if a related threshold value is reached. The threshold values are set in several P registers (see VHFWLRQ page 71). TUCdiff is the difference between the transmitted cells of the PM originating point and the received cells of the PM terminating point. TUCdiff is calculated for the CLP-0+1 flow and TUCdiff0 for the CLP=0 flow. The BLER-0+1 counts the BIP16 errors of a block of user cells if no user cells are lost or misinserted, i.e. TUCdiff = 0.
Data Sheet
2-42
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
Common flow (CLP = 0+1)
(-2,X)
BLER0+1 (0,16) .... TUCdiff BLER0+1 X = not defined SECB = severely errored cell block MLOST = 3 Add 1 to IMPB (0,6) (0,5) (0,4) (0,3) (0,2) (0,1) MERR = 3 Add BIPV to ERRC MMISINS = 2 Add 1 to SECB Add 1 to SECBERR .... (-4,X) (-3,X) (-2,X) (-1,X) (0,0) (+1,X)(+2,X)(+3,X) .... Add 1 to SECB TUCdiff Add |TUCdiff| to LOSTC Add TUCdiff to MISC Add 1 to SECB Add |TUCdiff| to TLOSTC Add 1 to IMPB
Add 1 to SECBMIS Add 1 to IMPB
)LJXUH
30 'DWD &ROOHFWLRQ
1RWH7KH WKUHVKROGV 0/267 DQG 00,6,16 DQG 0(55 FDQ EH SURJUDPPHG IRU XS DQG GRZQVWUHDP GLUHFWLRQ VHSDUDWHO\ 7KH\ DSSO\ IRU DOO FRQQHFWLRQV
6LPXOWDQHRXV 30 IORZV The PXB 4340 AOP contains 128 PM processors which may be used to generate an FM flow or to terminate an FM flow. Terminating an FM flow means analyzing and looping of the FM cells as BR cells. During one cell cycle IRXU PM processors can be executed arbitrary for F4 and F5 level. It may happen that a user cell belongs to a VCC for which F5 segment PM is done. E.g. in the example of ILJXUH node b could be a VCC Originating Segment Point (OSP) in addition to the VPC TEP. In this case the arrival of a VCC user cell triggers two PM processors in the upstream part of the PXB 4340 AOP. In case of F4 and F5 segments e.g. the downstream part of a PXB 4340 AOP could be configured as VPC OSP and VCC OSP (UHIHU WR WDEOH ). In this case a user cell not only triggers two PM processors simultaneously, but might also complete two PM blocks. Then two FM cells have to be generated simultaneously. In this case the PXB 4340 AOP first inserts the VP-FM cell and then the VC-FM cell.
Data Sheet
2-43
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
$GMDFHQW 30 6HJPHQWV The arbitrary assignment of PM processors to connections also allows e.g. to terminate a Segment PM flow and generate a new Segment PM flow for the same connection within one PXB 4340 AOP as shown in ILJXUH .
QHAS6H !&
Segment FM flow
Segment FM flow
Segment BR flow
30 SURFHVVRU [ LQ DQDO\]H PRGH
PM entry
PM entry
30 SURFHVVRU \ LQ JHQHUDWH PRGH
98AS6H !&
x, y, z independent, any value between 0 and 127
DC entry
'& SURFHVVRU ]
Segment BR flow
PM = Performance Monitoring DC = Data Collection
)LJXUH
([DPSOH IRU DGMDFHQW 30 6HJPHQWV
$FWLYDWLRQ DQG 'HDFWLYDWLRQ &HOOV
These cell types are generated by the microprocessor and transmitted via the cell insertion function (VHFWLRQ ) of the PXB 4340 AOP. The detection and extraction of activation/deactivation cells is done automatically at the respective segment or end-to-end points if the PXB 4340 AOP is configured correctly and the function is enabled (which is possible per connection). Extracted cells are stored in the receive buffer (VHFWLRQ ). ,QWHUDFWLRQV EHWZHHQ 2$0 )XQFWLRQV
The PXB 4340 AOP does failure propagation automatically, e.g. a received VP-AIS cell automatically leads to the generation of VC-AIS and VP-RDI cells at the VP endpoint. Also the generation of AIS/RDI as a consequence of LOC state is done automatically. Failure propagation from degraded performance, detected with the PM function, to AIS/RDI insertion, however is not done automatically, but must be initiated by the microprocessor. To enforce VP-level AIS/RDI insertion command bits are available per connection. If enabled the PXB 4340 AOP automatically inserts VC-AIS cells for all VCCs of a VPC. Connection specific AIS state is left when user or CC cells are detected. Only end-to-end cells may react in this way with AIS because "shorter" CC flows such as segment CC or ICC may cause a mixture of AIS and SCC/ICC cells which would corrupt AIS recognition in the cases a)
Data Sheet 2-44 04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
and b) outlined in figure X. Consequently the AIS analyser implementation totally ignores SCC/ ICC cells. Neither the occurrence of SCC/ICC cells causes return to AIS normal state nor the setup for activation of the CC checker disables return to AIS normal state by a timeout criterion.
a)
OEP
OSP
TSP
TEP
user cells
AIS cells CC flow active
SCC cells
AIS monitoring corrupted if AIS state is left with SCC occurence TSP+TEP
b)
OEP
OSP
user cells
AIS cells CC flow active
SCC cells
RDI generating corrupted if AIS state is left with SCC occurence TSP+TEP
c)
OEP
OSP
AIS cells CC flow broken E2E-CC cells Undisturbed monitoring and TEP processing
AOPE
defect
E2E = End-to-End SCC = Segment CC
)LJXUH
(IIHFW RI && FHOOV RQ $,6 UHFRJQLWLRQ
Data Sheet
2-45
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
&HOO )LOWHUV
The PXB 4340 AOP provides two types of cell filters: * filters for special OAM cells * filters for general purpose ATM cells For both filter types two filters are provided. 6SHFLDO 2$0 &HOO )LOWHUV For these filters only the first payload byte of the desired OAM cell (OAM type and function type field) has to be programmed. The other criteria of OAM cells, VCI or PT coding are hard-wired in the chip. All OAM cells, F4 and F5, segment and end-to-end are detected. The filters are working for up- and downstream direction. For each filter the action upon the detection of an OAM cell of the programmed type can be programmed: * ignore cell (default) * discard cell * extract to receive buffer * copy to receive buffer and forward. Applications for this filter function are e.g. proprietary OAM functions using the standardized System OAM cell coding or the treatment of future OAM cell types. *HQHUDO SXUSRVH &HOO )LOWHUV These filters consist of 3 programmable words for the comparison of all 5 cell header bytes plus the first payload byte. The UTOPIA cell format described in VHFWLRQ is compared. Each bit can be individually masked with the mask pattern defined in 3 programmable mask registers. A masked bit matches always when the pattern is compared to the ATM cells. Cells from both upand downstream direction are compared. Upon match the following actions can be selected: * ignore cell (default); e.g. forward cell * discard cell * extract to receive buffer * copy to receive buffer and forward. See VHFWLRQ for the receive buffer description. In addition to the these actions the match signals of both comparators and for up- and downstream direction are output at four pins as a short pulse. The pulses can be further processed by external logic. This feature could be used for measurements. Other applications for the general purpose cell filters are e.g. communication channels within a switch or the filtering of RM cells. 0LFURSURFHVVRU &RQWURO
A 16-bit microprocessor interface for embedded controllers like e.g. the 386EX is provided for configuration and operation of the PXB 4340 AOP. 8 address lines allow to address 172 registers (non-contiguous addresses). Interrupts are provided for the notification of unexpected events. DMA support is provided for fast data transfer to and from the external RAMs.
Data Sheet
2-46
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
$FFHVV WR LQWHUQDO DQG H[WHUQDO 5$0V
The microprocessor can not access these RAMs directly, but uses a transfer register set. It consists of three blocks: * read register block * write register block * mask register block. In addition an address register specifying the entry to be accessed and a command register to specify the RAM and to start the transfer are defined. The PXB 4340 AOP uses one single access type, the read-modify-write transfer, where the old data is transferred from the specified RAM entry to the Read Transfer Registers and the contents of the Write Transfer Registers are written to the RAM entry for those bits which are unmasked. In addition to the read-modify-write access executed upon microprocessor command for a single entry, there are two other access types to the external RAM (figure 30): * the access initiated by the passing ATM cell * the SCAN access for OAM and/or DMA.
internal or external RAM
$23 5HJLVWHUV
RAM entry n
select
Mask Registers
RAM entry k
write M U X
rea d
Write Transfer Registers
Data Read Transfer Registers
3
Address
RAM entry 0 transfer command Address = k
CMR Register Address Register
)LJXUH
$FFHVV WR LQWHUQDO RU H[WHUQDO 5$0V
Data Sheet
2-47
04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
6&$1 0HFKDQLVP ZLWK 2$0 DQGRU '0$ )XQFWLRQ
This mechanism has to be triggered by the microprocessor. It is recommended to trigger it in a 0.5 s time frame, as all time-out values are determined based on this time interval. During a SCAN all entries within the specified range of the external RAMs are accessed sequentially using the read-modify-write access described in VHFWLRQ . The SCAN must be programmed in a way that it covers all used RAM entries in a little less than 0.5 s. To initialize the SCAN mechanism use register SCCONF2 (see VHFWLRQ page 79). The SCAN is processed for all connections inside the range selected by register SCCONF4 (see VHFWLRQ page 80) and register SCCONF5 (see VHFWLRQ page 81). To initiate the SCAN bit STARTSC in register SCCONF3 has to be set (see VHFWLRQ page 80). The following equation can be used to calculate the scan cycle period (SCP) : f Core ( scanperiod - tolerance ) x -----------------------------------cycles per cell SCP = -----------------------------------------------------------------------------------------------------------------LCI max - LCI min + 1 with : scanperiod + tolerance < 500 ms ! Example : The AOP needs 32 cycles per cell. At a core frequency of 51.84 MHz the AOP can process 1.62 M cells per second. If SCAN has to process e.g. 8192 connections within 350 ms (scanperiod + tolerance) the SCP is calculated as : cells 350ms x 1.62 M -----------s SCP = ------------------------------------------------------------ = 69.21 cells 8192 Here SCP is equal to the time the AOP needs to process 69.21 cells. The values of the register entry SCP is of type integer. So the SCP is rounded to 69. If the result of the SCP calculation is 40 or less SCAN operation is no more guaranteed at full traffic load because SCAN operation requires a number of empty cycles. With each SCAN trigger two functions can be enabled independently for up- and downstream direction: OAM function and DMA transfers. OAM functions include all the necessary actions for AIS/RDI/CC processing, i.e. update of counters, check for time-out values and execution of state transitions, OAM cell insertions and interrupts. The DMA function allows to transfer data to and from the external RAM during the SCAN. The DMA function has two modes, the normal DMA function and the compressed DMA. In the normal DMA mode a specified dword of each external RAM entry is transferred to a range of the microprocessor main memory. Each bit of the specified dword can be overwritten by a specified value for all entries. So the normal DMA can be used to initialize the whole external RAM to common values or also to verify entries of all connections. In compressed DMA mode one dword with pre-defined bits collected from several dwords of the external RAM is transferred to a microprocessor memory range. The pre-defined bits are status bits and status transition bits. The status transition bits must be reset with each SCAN, which can be achieved with appropriate settings of write and mask registers. The compressed DMA is typically used in-service together with the OAM function (see VHFWLRQ ).
Data Sheet 2-48 04.2000
3;% (
)XQFWLRQDO 'HVFULSWLRQ
For the DMA data transfers a 32 word FIFO is provided on-chip for DMA read (figure 31). It is emptied by the microprocessor via consecutive reads of the DMA register. The DMA request pin of the PXB 4340 AOP is asserted when the FIFO is occupied and deasserted when it is empty. The DMA transfer itself must be executed by an external DMA controller.
external AOP RAM up or down entry k
AOP
cell access
SCAN / OAM DMA-Option
P access transfer registers
32 x 16 bit words FIFO
DMAR register
P - i/f
)LJXUH
6FDQ 0HFKDQLVP ZLWK 2$0 DQGRU '0$ )XQFWLRQ
5HFHLYH DQG 7UDQVPLW %XIIHU
The PXB 4340 AOP provides a 12-cell receive buffer and a 1-cell transmit buffer. They are used for insertion and extraction of LB cells, activation and deactivation cells and special cells defined with the cell filters (see VHFWLRQ ). The buffers are realized differently. The transmit buffer consists of 27 words, directly addressable by the microprocessor for read and write. When the cell is assembled it can be inserted by setting a command bit. The command bit is reset after complete insertion of the cell into the data stream. The insertion direction, up- or downstream can be selected and also if the CRC-10 should be computed automatically by the chip or not. The receive buffer is realized as FIFO with word-wise access via a single register. A cell is read with 27 consecutive read accesses to this register. Reception of a cell is signalled to the microprocessor via an interrupt bit. The interrupt bit is reset by the chip automatically after the last read access if no more cell is in the buffer. The receive buffer collects cells from up- and downstream direction, they are distinguished with a bit in the UDF2 octet. Cell format for both receive and transmit buffer is the 16-bit UTOPIA format as described in VHFWLRQ .
Data Sheet 2-49 04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7DEOH DGU KH[
5HJLVWHU 'HVFULSWLRQ $23 5HJLVWHU 2YHUYLHZ UHJLVWHU GHVFULSWLRQ
$6,& FRUH
3
UHVHW YDOXH
VHH SDJH
5HDG0DVN:ULWH 5HJLVWHUV 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A WDR0L WDR0H WDR1L WDR1H WDR2L WDR2H WDR3L WDR3H WDR4L WDR4H WDR5L WDR5H WDR6L WDR6H WDR7L WDR7H WDR8L WDR8H WDR9L WDR9H WDR10L WDR10H WDR11L WDR11H WDR12L WDR12H WDR13L Write Data Register 0 (15.. 0) Write Data Register 0 (31..16) Write Data Register 1 (15.. 0) Write Data Register 1 (31..16) Write Data Register 2 (15.. 0) Write Data Register 2 (31..16) Write Data Register 3 (15.. 0) Write Data Register 3 (31..16) Write Data Register 4 (15.. 0) Write Data Register 4 (31..16) Write Data Register 5 (15.. 0) Write Data Register 5 (31..16) Write Data Register 6 (15.. 0) Write Data Register 6 (31..16) Write Data Register 7 (15.. 0) Write Data Register 7 (31..16) Write Data Register 8 (15.. 0) Write Data Register 8 (31..16) Write Data Register 9 (15.. 0) Write Data Register 9 (31..16) Write Data Register 10 (15.. 0) Write Data Register 10 (31..16) Write Data Register 11 (15.. 0) Write Data Register 11 (31..16) Write Data Register 12 (15.. 0) Write Data Register 12 (31..16) Write Data Register 13 (15..0) r r r r r r r r r r r r r r r r r r r r r r r r r r r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59 59
Data Sheet
3-50
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7DEOH DGU KH[ 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38
$23 5HJLVWHU 2YHUYLHZ UHJLVWHU GHVFULSWLRQ WDR13H RDR0L RDR0H RDR1L RDR1H RDR2L RDR2H RDR3L RDR3H RDR4L RDR4H RDR5L RDR5H RDR6L RDR6H RDR7L RDR7H RDR8L RDR8H RDR9L RDR9H RDR10L RDR10H RDR11L RDR11H RDR12L RDR12H RDR13L RDR13H MDR0L Write Data Register 13 (31..16) Read Data Register 0 (15.. 0) Read Data Register 0 (31..16) Read Data Register 1 (15.. 0) Read Data Register 1 (31..16) Read Data Register 2 (15.. 0) Read Data Register 2 (31..16) Read Data Register 3 (15.. 0) Read Data Register 3 (31..16) Read Data Register 4 (15.. 0) Read Data Register 4 (31..16) Read Data Register 5 (15.. 0) Read Data Register 5 (31..16) Read Data Register 6 (15.. 0) Read Data Register 6 (31..16) Read Data Register 7 (15.. 0) Read Data Register 7 (31..16) Read Data Register 8 (15.. 0) Read Data Register 8 (31..16) Read Data Register 9 (15.. 0) Read Data Register 9 (31..16) Read Data Register 10 (15.. 0) Read Data Register 10 (31..16) Read Data Register 11 (15.. 0) Read Data Register 11 (31..16) Read Data Register 12 (15.. 0) Read Data Register 12 (31..16) Read Data Register 13 (15.. 0) Read Data Register 13 (31..16) Mask Data Register 0 (15.. 0)
$6,& FRUH r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r
3 rw r r r r r r r r r r r r r r r r r r r r r r r r r r r r rw
UHVHW YDOXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
VHH SDJH 59 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60
Data Sheet
3-51
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7DEOH DGU KH[ 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48
$23 5HJLVWHU 2YHUYLHZ UHJLVWHU GHVFULSWLRQ MDR0H MDR1L MDR1H MDR2L MDR2H MDR3L MDR3H MDR4L MDR4H MDR5L MDR5H MDR6L MDR6H WMASK RMWC RMWADR Mask Data Register 0 (31..16) Mask Data Register 1 (15.. 0) Mask Data Register 1 (31..16) Mask Data Register 2 (15.. 0) Mask Data Register 2 (31..16) Mask Data Register 3 (15.. 0) Mask Data Register 3 (31..16) Mask Data Register 4 (15.. 0) Mask Data Register 4 (31..16) Mask Data Register 5 (15.. 0) Mask Data Register 5 (31..16) Mask Data Register 6 (15.. 0) Mask Data Register 6 (31..16) Mask for word 7-13 RMW Control Register LCI/PM pointer for RMW
$6,& FRUH r r r r r r r r r r r r r r rw r
3 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
UHVHW YDOXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
VHH SDJH 60 60 60 60 60 60 60 60 60 60 60 60 60 61 62 63
&HOOW\SH 5HFRJQLWLRQ 5HJLVWHUV 60 61 62 63 64 65 66 67 68 69 6A 6B 6C
Data Sheet
LSIDR0 LSIDR1 LSIDR2 LSIDR3 LSIDR4 LSIDR5 LSIDR6 LSIDR7 CTR0 CTR1 CTR10 CTR11 CTR12
LB location/source identifier LB location/source identifier LB location/source identifier LB location/source identifier LB location/source identifier LB location/source identifier LB location/source identifier LB location/source identifier Special OAM cell filter 0 Special OAM cell filter 1 Cell filter1 Cell filter1 Cell filter1
3-52
r r r r r r r r r r r r r
rw rw rw rw rw rw rw rw rw rw rw rw rw
0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
64 64 64 64 64 64 64 64 64 64 65 65 65
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7DEOH DGU KH[ 6D 6E 6F 70 71 72 73 74 75
$23 5HJLVWHU 2YHUYLHZ UHJLVWHU GHVFULSWLRQ CTR20 CTR21 CTR22 MR10 MR11 MR12 MR20 MR21 MR22 Cell filter2 Cell filter2 Cell filter2 Mask for cell filter 1 Mask for cell filter 1 Mask for cell filter 1 Mask for cell filter 2 Mask for cell filter 2 Mask for cell filter 2
$6,& FRUH r r r r r r r r r
3 rw rw rw rw rw rw rw rw rw
UHVHW YDOXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
VHH SDJH 65 65 65 65 65 65 65 65 65
7UDQVPLW5HFHLYH5HJLVWHUV 80 81 82 83 : : 9A 9C 9D TXR0 TXR1 TXR2 TXR3 : : TXR26 TMCR RXRCEL Transmit Cell Register 0 (Header) Transmit Cell Register 1 (Header) Transmit Cell Register 2 (Header) Transmit Cell Register 3 (Payload) : : Transmit Cell Register 26 (Payload) Tx Command Register Receive Cell Buffer r r r r : : r rw w rw rw rw rw : : rw rw r 0000H 0000H 0000H 0000H :
:
67 67 67 68 : : 68 69 70
0000H 0000H 0000H
3HUIRUPDQFH 0RQLWRULQJ 5HJLVWHUV A0 A1 A2 A3 A4 A5 A6 A7 UMLOST UMMISINS UMLOST0 UMERR DMLOST DMMISINS Upstream Max. Lost cells Upstream Max. Misinserted cells Upstream Max. Lost CLP0 cells Upstream Max. Errors Downstream Max. Lost cells Downstream Max. Misinserted cells Downstream Max. Errors r r r r r r r r rw rw rw rw rw rw rw rw 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 71 71 71 71 72 72 72 72
DMLOST0 Downstream Max. Lost CLP0 cells DMERR
Data Sheet
3-53
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7DEOH DGU KH[
$23 5HJLVWHU 2YHUYLHZ UHJLVWHU GHVFULSWLRQ
$6,& FRUH
3
UHVHW YDOXH
VHH SDJH
6FDQ 5HJLVWHUV B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF DWDRL DWDRH DMRL DMRH PHYERRL PHYERRH DMAR DCONF SCCONF0 SCCONF1 SCCONF2 SCCONF3 SCCONF4 SCCONF5 SCSTAT0 SCSTAT1 DMA Write-Register (15..0) DMA Write-Register (31..16) DMA Mask-Register (15.. 0) DMA Mask-Register (31..16) Port 15..0 upstream only Port 23..16 upstream only DMA-Register of DMA-FIFO DMA configuration register OAM timeout values OAM timeout values SCAN cycle period/tolerance SCAN command register SCAN start LCI SCAN end LCI SCAN status register 0 SCAN status register 1 r r r r r r rw r r r r r r r rw rw rw rw rw rw rw rw r rw rw rw rw rw rw rw r r 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0275H 0057H 002DH 0000H 0000H 0000H 0000H 8000H 74 74 75 75 76 76 77 77 78 79 79 80 80 81 81 82
Data Sheet
3-54
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7DEOH DGU KH[
$23 5HJLVWHU 2YHUYLHZ UHJLVWHU GHVFULSWLRQ
$6,& FRUH
3
UHVHW YDOXH
VHH SDJH
,QWHUUXSW 5HJLVWHUV D0 D1 D2 D3 D4 D5 ISR0 ISR1 IMR0 IMR1 CIFL CIFH Interrupt Status Register 0 Interrupt Status Register 1 Interrupt Mask Register 0 Interrupt Mask Register 1 Cell Insertion Fault Port bit map (downstream) rw rw r r rw rw rw rw rw rw r r 0000H 0000H 0000H 0000H 0000H 0000H 83 84 85 85 85 85
8WRSLD &RQILJXUDWLRQ 5HJLVWHUV E0 E1 E2 E3 E4 E5 E6 E7 E8 UTCONF0 UTCONF1 UPRTENL UPRTENH DPRTENL DPRTENH OAMTHRU OAMTHRD BPTHRD Config. UTOPIA ATM side Config. UTOPIA PHY side UTOPIA port 23..0 enable upstream UTOPIA port 23..0 enable downstream Threshold for forced OAM cell insertion upstream Threshold for cell insertion downstream Queue backpressure level downstream r r r r r r r r r rw rw rw rw rw rw rw rw rw 0000H 0000H 0000H 0000H 0000H 0000H 001EH 0060H 0060H 87 88 89 89 89 90 90 91 91
Data Sheet
3-55
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7DEOH DGU KH[
$23 5HJLVWHU 2YHUYLHZ UHJLVWHU GHVFULSWLRQ
$6,& FRUH
3
UHVHW YDOXH
VHH SDJH
0LVFHOODQHRXV 5HJLVWHUV F0 F1 F2 F3 F4 F5 F6 F7 F8 MISC TESTR1 TESTR2 VERL VERH BISTML BISTMH BISTDON BISTERR SW reset, 1Mbit/2Mbit RAM Test register 1 Test register 2 Version register (15.. 0) Version register (31..16) BIST Mode Low register BIST Mode High register BIST Done BIST Error rw, r r r r r rw rw rw rw rw r r rw rw r r 0000H 0000H 0000H A06DH 523BH 0000H 0000H 0000H 0000H 92 92 93 94 94 95 95 96 97
Data Sheet
3-56
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7UDQVIHU 5HJLVWHUV
These registers are provided for data transfer to and from the external connection RAMs or the internal RAMs.Two internal RAMs are provided, one for PM data processing and one for the collection of analysed PM results. Both PM RAMs are shared for up- and downstream direction. The entries in each RAM have different sizes as shown in 7DEOH . 7DEOH 5$0 W\SH ,QWHUQDO DQG H[WHUQDO 5$0V /RFDWLRQ External External On-chip On-chip 1XPEHU RI HQWULHV 4 - 16k* 4 - 16k* 128 128 'ZRUGV SHU HQWU\ 8 8 3 14
Upstream connection RAM Downstream connection RAM PM processing data PM data collection
* Depending on external RAM size
There is only one single RAM access type, the read-modify-write transfer shown in ILJXUH . It consists of two steps: in the first step all data from the specified RAM entry is transferred into the read register set RDR. In the second step the data is written back again. It can be either the original data or new data specified in the write register set WDR. The decision if original or new data is written to the RAM entry is done via the mask register set MDR and the mask register WMASK. For the lower 7 Dwords of an entry the source of each single bit can be individually selected by the corresponding bit of the respective MDR register (bit-by-bit basis), for the upper 7 Dwords one single bit of WMASK selects the source for a whole Dword.
Data Sheet
3-57
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
RAM entry k 1 Read Transfer 2 Write Transfer 32 3 2 1 32 0
1 32 Select 13 Read Transfer Registers RDR 0 H L H L Write Transfer Registers WDR 0 13 WMASK Bit 0..6 07 Mask Registers 6 MDR 0 H L 6 13
)LJXUH
5HDGPRGLI\ZULWH 7UDQVIHU
The address of the selected entry is given in register RMWADR. Register bits for specifying the target RAM and initiating the transfer are contained in the read-modify-write control register RMWC. This register also contains command bits for setting or clearing all mask register bits. Read and write register sets RDR and WDR contain 14 Dwords in 28 registers. For simplification the mask register set is slightly different: MDR0..6 have a one-to-one bit mapping with RDR0..6 and WDR0..6. For RDR7..13 and WDR7..13 one single mask bit for each Dword is provided in the WMASK register, bits 0..6. When accessing RAM entries with less than 14 Dwords (see 7DEOH ) only the lower registers of RDR, WDR and MDR are involved, e.g. for accesses to the 8-Dword size entries of the external connection tables RDR0..7, WDR0..7, MDR0..6 and bit 0 of WMASK are involved. For accesses to the different RAMs the RDR and WDR register bits have different meaning. This is described for each target RAM in the mapping tables (see VHFWLRQ ).
Data Sheet
3-58
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
:ULWH 7UDQVIHU 5HJLVWHUV :'5/:'5+ Read/write Address 00H..1BH Value after reset 0000H The write transfer registers are shown below with their mapping to the 32-bit Dwords 0..13. Dword
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register WDR13H / Address 1BH Register WDR12H / Address 19H Register WDR11H / Address 17H Register WDR10H / Address 15H Register WDR9H / Address 13H Register WDR8H / Address 11H Register WDR7H / Address 0FH Register WDR6H / Address 0DH Register WDR5H / Address 0BH Register WDR4H / Address 09H Register WDR3H / Address 07H Register WDR2H / Address 05H Register WDR1H / Address03H Register WDR0H / Address 01H
Register WDR13L / Address 1AH Register WDR12L / Address 18H Register WDR11L / Address 16H Register WDR10L / Address 14H Register WDR9L / Address 12H Register WDR8L / Address 10H Register WDR7L / Address 0EH Register WDR6L / Address 0CH Register WDR5L / Address 0AH Register WDR4L / Address 08H Register WDR3L / Address 06H Register WDR2L / Address 04H Register WDR1L / Address 02H Register WDR0L / Address 00H
When accessing the external RAM bit 31 of each Dword controls the parity bit of the entry. If bit 31=0 the correct parity bit is generated. If bit 31=1 the parity bit is inverted.
Data Sheet
3-59
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
5HDG 7UDQVIHU 5HJLVWHUV 5'5/5'5+ Read Address 1CH..37H Value after reset 0000H The read transfer registers are shown below with their mapping to the 32-bit Dwords 0..13. Dword
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register RDR13H / Address 37H Register RDR12H / Address 35H Register RDR11H / Address 33H Register RDR10H / Address 31H Register RDR9H / Address 2FH Register RDR8H / Address 2DH Register RDR7H / Address 2BH Register RDR6H / Address 29H Register RDR5H / Address 27H Register RDR4H / Address 25H Register RDR3H / Address 23H Register RDR2H / Address 21H Register RDR1H / Address 1FH Register RDR0H / Address 1DH
Register RDR13L / Address 36H Register RDR12L / Address 34H Register RDR11L / Address 32H Register RDR10L / Address 30H Register RDR9L / Address 2EH Register RDR8L / Address 2CH Register RDR7L / Address 2AH Register RDR6L / Address 28H Register RDR5L / Address 26H Register RDR4L / Address 24H Register RDR3L / Address 22H Register RDR2L / Address 20H Register RDR1L / Address 1EH Register RDR0L / Address 1CH
When reading the external RAM bit 31 contains the result of the parity check. Bit 31=0 indicates that the external parity bit stored in bit 31 was correct, bit 31=1 indicates a wrong parity bit. 0DVN 'DWD 5HJLVWHUV 0'5/0'5+ Read/write Address 38H..45H Value after reset 0000H These registers have a bit-to-bit correspondence to the 7 lower read and write transfer registers RDR0..RDR6 and WDR0..WDR6. If a bit in MDR0L..MDR6H is cleared, the corresponding bit of the RAM entry remains unchanged, if set the RAM entry bit is overwritten by the value contained in the corresponding write register bit. The upper 7 transfer registers are masked globally with one bit each. These bits are contained in the WMASK register.
Data Sheet
3-60
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
The mask data registers are shown below with their mapping to the 32-bit Dwords 0..6. Dword
6 5 4 3 2 1 0
Register MDR6H / Address 45H Register MDR5H / Address 43H Register MDR4H / Address 41H Register MDR3H / Address 3FH Register MDR2H / Address 3DH Register MDR1H / Address 3BH Register MDR0H / Address 39H
Register MDR6L / Address 44H Register MDR5L / Address 42H Register MDR4L / Address 40H Register MDR3L / Address 3EH Register MDR2L / Address 3CH Register MDR1L / Address 3AH Register MDR0L / Address 38H
:ULWH 0DVN 5HJLVWHU :0$6. Read/write Address 46H Value after reset 0000H Unused Unused Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mask for Dword 13. Mask for Dword 12. Mask for Dword 11. Mask for Dword 10. Mask for Dword 9. Mask for Dword 8. Mask for Dword 7.
Data Sheet
3-61
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
5HDG0RGLI\:ULWH &RQWURO 5HJLVWHU 50:& Read/write Address 47H Value after reset 0000H Unused Unused RAMSEL(1:0) START UP/DN WRA RDA
RAMSEL(1:0)
Select RAM for RMW access 00 01 1x PM data processing RAM External RAM (up- or downstream selected with bit 2). PM data collection RAM
START
Command bit. Set =1 to start the RMW-access specified with bits 2, 4 and 5. Bit 3 is reset after execution of the command. RDR registers should not be read before, otherwise it will result in unexpected values. Selection of external RAM for RMW-Access: 0 1 Downstream-RAM. Upstream-RAM.
UP/DN
WRA
Write all. Setting this bit together with the START bit sets all mask register bits to one EHIRUH the RMW access. This results in a write access of the whole entry. All Dwords of the specified entry are overwritten. The mask bits remain cleared after the access. WRA is reset to zero after execution of the RMW access. Read all. Setting this bit together with the START bit sets all mask register bits to zero EHIRUH the RMW access. This results in a read only access. No data in the specified entry is modified. The mask bits remain set after the access. RDA is reset to zero after execution of the RMW access.
RDA
1RWH 7KH VHOHFW ELWV 5$06(/ UP/DN DQG 5'$ RU :5$ FDQ EH VHW WRJHWKHU ZLWK WKH 67$57 ELW LQ WKH VDPH ZULWH DFFHVV 1RWH 5'$ DQG :5$ PXVW QRW EH VHW VLPXOWDQHRXVO\ 1RWH 5HJLVWHU 50:& LV ZULWH SURWHFWHG DV ORQJ DV 67$57 LV VHW
Data Sheet
3-62
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
5HDG0RGLI\:ULWH $GGUHVV 5HJLVWHU 50:$'5 Read/write Address 48H Value after reset 0000H Unused ADR(7:0) ADR(13:8)
ADR(13:0)
Specifies the base address for the RMW access. In 4x1M mode the bits 13..12 selects the RAM, the bits 11..0 defines the address. In 2x2M mode the bit 13 selects the RAM and the bits 12..0 defines the address. Should not be outside the physical range of the respective RAM (see 7DEOH ).
1RWH 5HJLVWHU 50:$'5 LV ZULWH SURWHFWHG DV ORQJ DV WKH 67$57 ELW RI 50:& LV VHW
Data Sheet
3-63
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
5HJLVWHUV IRU &HOOW\SH 5HFRJQLWLRQ
/RFDWLRQ 6RXUFH ,GHQWLILHU 5HJLVWHUV /6,'5 Read/write Address 60H..67H Value after reset 0000H $GGU 60 61 62 63 64 65 66 67 1DPH LSIDR0 LSIDR1 LSIDR2 LSIDR3 LSIDR4 LSIDR5 LSIDR6 LSIDR7 Port ID byte #15 Port ID byte #13 Port ID byte #11 Port ID byte #9 Port ID byte #7 Port ID byte #5 Port ID byte #3 Port ID byte #1 Port ID byte #14 Port ID byte #12 Port ID byte #10 Port ID byte #8 Port ID byte #6 Port ID byte #4 Port ID byte #2 Port ID byte #0
The 16-octet Port ID defines a unique identifier for the switch port. It is used for intra-domain LB cells. Depending on layer point configuration and settings the Port ID is compared with Location or Source ID of the LB cell. 6SHFLDO 2$0 &HOO )LOWHU &75 &75 Read/write Address 68H..69H Value after reset 0000H Both CTR0 and CTR1 have the same mapping: Unused OAMTYP(3:0) FUNCTYP(3:0) ACTION(1:0)
Using these registers two OAM cell types can be defined. OAM cells in the cell stream which match a programmed pattern are treated according to the four options defined in the corresponding ACTION(1:0) bits. The action is executed for all matching cells in up- and downstream direction. This function is provided to support new or proprietary OAM cell types. These could be dropped to the microprocessor and handled by SW. Recognized as OAM cells are: all cells with either PTI=100 or 101 or VCI=3 or 4 and which have the correct CRC-10. OAM cells with incorrect CRC-10 are discarded anyway with notification in interrupt status register ISR0 and additionally an indication in the external connection RAM entry for the respective connection (LCI).
Data Sheet
3-64
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
ACTION(1:0)
Action in case of cell filter match 00 01 10 11 Ignore cell. Use this selection to disable the function. Discard cell. Drop cell; the cell is extracted from the cell stream and stored in the receive buffer. Monitor cell; the cell is copied into the receive buffer.
OAMTYP(3:0) FUNCTYP(3:0)
Defines the OAM Type bits of the OAM cell to be filtered. Defines the Function Type bits of the OAM cell to be filtered.
&HOO )LOWHU DQG 5HJLVWHUV &75[\ 05[\ Read/write Address 6AH..75H Value after reset 0000H Using these 12 registers two free programmable cell types can be filtered. The complete UTOPIA cell header (including 5 bits of the UDF1 octet but without the UDF2 octet) and the first payload octet are compared. Each bit within these six octets can be individually masked by setting the corresponding mask bit to one. Masked bits match anyway, unmasked bits must match with the corresponding bit in the passing cells. The programmed patterns are compared to all cells in up- and downstream direction. If all unmasked bits match one of the four actions defined in the action bits (8 and 9 of words CTRx2) is executed for the cell. This function can be used to treat selected cells by SW, e.g. by extracting them from the cell stream and processing them by SW. This could be OAM cells or any other type of cells, e.g. RM cells or internal message cells. In addition four pins are provided to indicate the match of filter 1 or 2 in up- and downstream direction. These detector pins are activated upon match if not disabled via ACTION(1:0)=00. 7DEOH &HOO )LOWHU 'HWHFWRU 2XWSXWV 0DWFK RI &HOO )LOWHU 'LUHFWLRQ 1 1 2 2 upstream downstream upstream downstream
$FWLYDWHG 3LQ FPCT1U FPCT1D FPCT2U FPCT2D
The match signals of the indication pins FPCTxy can be used e.g. to determine the CDV of a certain connection with external evaluation circuitry.
Data Sheet
3-65
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Programming of the two cell filters is identical:
cell type
VPI/LCI
VCI
PT C LCI HK UDF1
1st Payload
1 1 2 2
MR10 CTR10 MR20 CTR20
MR11 CTR11 MR21 CTR21
MR12 CTR12 MR22 CTR22
Only the 5 MSBs of the UDF1 octet are compared. The 3 LSBs are treated like masked and match always. In case of the proprietary cell format UDF1(7:3) contains the two MSBs of the LCI and the housekeeping bits. See )LJXUHV and for cell formats. CTRxy, MRxy Meaning of the indices x, y: x y Bit 10 of CTRx2 Bit 9,8 of CTRx2 Unused Define the action to be done in case of match: 00 01 10 11 Ignore cell. Use this selection to disable the function. Discard cell. Drop cell; the cell is extracted from the cell stream and stored in the receive buffer. Monitor cell; the cell is copied into the receive buffer. Selects filter 1 or filter 2. Selects one of the three registers for each filter.
Data Sheet
3-66
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7UDQVPLW 5HFHLYH 5HJLVWHUV
These registers are used to insert ATM cells into the cell stream and to extract or copy cells from the cell stream. For the insertion one set of 27 registers (TXR0...TXR26) is provided capable of storing a complete ATM cell in UTOPIA cell format. When assembled the ATM cell is inserted into either up- or downstream data stream via the command register TMCR. For cell extraction/ copy an internal 12-cell receive buffer is provided. A non-empty receive buffer is signalled via bit 9 of interrupt status register ISR0. Cells are read from the internal receive buffer by repeated reading of the RXRCEL register. 7UDQVPLW &HOO +HDGHU 5HJLVWHUV 7;5 Read/write Address 80H...82H Value after reset 0000H (for all) $GGU 80 81 82 1DPH TXR0 TXR1 TXR2 Header octet 1 Header octet 3 UDF1(7:0) Header octet 2 Header octet 4 UDF2(7:5) PN(4:0)
Header octets 1..4 as well as UDF1 and UDF2 octets are mapped transparently to the cell. The only field which is interpreted by the AOP is PN(4:0); it selects the (internal) PHY port number the cell is destined to. For the determination of the UTOPIA port number and header formats see VHFWLRQ . In case of 8-bit UTOPIA PN(4:0) is evaluated but not transferred to the data stream.
Data Sheet
3-67
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7UDQVPLW &HOO 3D\ORDG 5HJLVWHUV 7;57;5 Read/write Address 83H...9AH Value after reset 0000H (for all) $GGU 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 1DPH TXR3 TXR4 TXR5 TXR6 TXR7 TXR8 TXR9 TXR10 TXR11 TXR12 TXR13 TXR14 TXR15 TXR16 TXR17 TXR18 TXR19 TXR20 TXR21 TXR22 TXR23 TXR24 TXR25 TXR26 Payload octet 1 Payload octet 3 Payload octet 5 Payload octet 7 Payload octet 9 Payload octet 11 Payload octet 13 Payload octet 15 Payload octet 17 Payload octet 19 Payload octet 21 Payload octet 23 Payload octet 25 Payload octet 27 Payload octet 29 Payload octet 31 Payload octet 33 Payload octet 35 Payload octet 37 Payload octet 39 Payload octet 41 Payload octet 43 Payload octet 45 Payload octet 47 Payload octet 2 Payload octet 4 Payload octet 6 Payload octet 8 Payload octet 10 Payload octet 12 Payload octet 14 Payload octet 16 Payload octet 18 Payload octet 20 Payload octet 22 Payload octet 24 Payload octet 26 Payload octet 28 Payload octet 30 Payload octet 32 Payload octet 34 Payload octet 36 Payload octet 38 Payload octet 40 Payload octet 42 Payload octet 44 Payload octet 46 Payload octet 48
1RWH $GGUHVV %+ LV XQXVHG All octets are mapped transparently into the transmitted cell. In case the automatic CRC-10 generation is enabled the two LSBs of octet 47 and octet 48 will be overwritten. The 6 MSBs of octet 47 are mapped transparently into the cell. Hence to be conform to the standardized OAM cell format these bits must be programmed to zero before inserting an OAM cell.
Data Sheet
3-68
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7UDQVPLVVLRQ &RPPDQG 5HJLVWHU 70&5 Read/write Address 9CH Value after reset 0000H Unused Unused ENCRC TXUP TXDN
ENCRC
Enable automatic CRC-10 generation of inserted cell 0 1 No automatic CRC10. Must be provided by P. CRC10 automatically generated by AOP. It is inserted into payload octets 47 and 48 (see VHFWLRQ ).
TXUP
Writing this bit to 1 initiates insertion of the cell specified in registers 80...9A into upstream data path. Insertion is done with the next available free cell cycle. After completed insertion TXUP is reset. Writing this bit to 1 initiates insertion of the cell specified in registers 80H...9AH into the downstream data path. Insertion is done with the next available free cell cycle. After completed insertion TXDN is reset.
TXDN
1RWH ,W LV QRW SRVVLEOH WR VHW ERWK 7;83 DQG 7;'1 VLPXOWDQHRXVO\ 7;83 ZLOO EH VHW 1RWH 7KH FHOO WUDQVPLW UHJLVWHUV 7;5 DQG WKH WUDQVPLW FRPPDQG UHJLVWHU 70&5 LWVHOI DUH ZULWH SURWHFWHG DV ORQJ DV RQH RI WKH LQVHUWLRQ FRPPDQG ELWV 7;83 RU 7;'1 LV VHW 7KLV DYRLGV HUURQHRXV PRGLILFDWLRQ RI WKH FHOO GXULQJ WKH WUDQVPLVVLRQ SKDVH
Data Sheet
3-69
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
5HFHLYH &HOO %XIIHU 5HDG 5HJLVWHU 5;5&(/ Read Address 9DH Value after reset 0000H RXRCEL(15:8) RXRCEL(7:0)
RXRCEL(15:0)
Receive Cell Buffer access. A cell extracted or copied from the data stream is transferred from the internal receive buffer to the microprocessor by 27 read accesses of RXRCEL. The accesses need not be consecutive; it is allowed to access other registers in between. Received cell(s) are indicated with bit 9 of ISR0 set. After read-out of the last cell ISR0(9) is reset by the AOP.
Cell format of the extracted cell is: 5HDG $FFHVV 1st access 2nd access 3rd access 4th access : : 27th access Header octet 1 Header octet 3 UDF1(7:0) Payload octet 1 : : Payload octet 47 7 6 Header octet 2 Header octet 4 UDF2(5:0) Payload octet 2 : : Payload octet 48
The cell format is identical to the insertion cell format except the UDF2 octet: Bit 7 Bit 6 UDF2(7) of the extracted cell (don't care in case of 8-bit UTOPIA) Source of the received cell (overwrites UDF2(6) of extracted/copied cell) : 0 1 UDF2(5:0) Cell from downstream direction Cell from upstream direction
6 LSBs of the UDF2 octet of the extracted cell (don't care in case of 8bit UTOPIA).
Data Sheet
3-70
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
3HUIRUPDQFH 0RQLWRULQJ &RQILJXUDWLRQ 5HJLVWHUV
These registers define the thresholds in the PM data collection algorithm described in ILJXUH 26. The referenced counters are located in the PM Data Collection RAM (see VHFWLRQ 3.9.6). 8SVWUHDP 0D[LPXP /RVW FHOOV 80/267 Read/write Address A0H Value after reset 0000H Recommended value 0003H. UMLOST(15:0) holds the global MLOST threshold (CLP0+1 cells) for the PM data collection in upstream direction. A PM block with more than MLOST lost cells is considered severely errored by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal MLOST cells are missing the lost cell counters are incremented. 8SVWUHDP 0D[LPXP 0LVLQVHUWHG FHOOV 800,6,16 Read/write Address A1H Value after reset 0000H Recommended value 0002H. UMISINS(15:0) holds the global MMISINS threshold for the PM data collection in upstream direction. A PM block with more than MMISINS misinserted cells is considered severely errored by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal MMISINS cells are misinserted the misinserted cell counters are incremented. 8SVWUHDP 0D[LPXP /RVW &/3 FHOOV 80/267 Read/write Address A2H Value after reset 0000H Recommended value 0003H. UMLOST0(15:0) holds the global MLOST0 threshold (CLP0 cells only) for the PM data collection in upstream direction. A PM block with more than MLOST0 lost cells is considered severely errored by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal MLOST0 cells are missing the lost cell counters are incremented. 8SVWUHDP 0D[LPXP (UURUV 80(55 Read/write Address A3H Value after reset 0000H Recommended value 0003H. UMERR(15:0) holds the global MERR threshold for the PM data collection in upstream direction. A BR cell carrying a block error result BLER value greater than MERR denotes a severely errored block. Accordingly the SECB counter is incremented. If BLER is less or equal MERR the BLER value is added to the error counter ERRC.
Data Sheet
3-71
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
'RZQVWUHDP 0D[LPXP /RVW FHOOV '0/267 Read/write Address A4H Value after reset 0000H Recommended value 0003H. DMLOST(15:0) holds the global MLOST threshold (CLP0+1 cells) for the PM data collection in downstream direction. A PM block with more than MLOST lost cells is considered severely errored by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal MLOST cells are missing the lost cell counters are incremented. 'RZQVWUHDP 0D[LPXP 0LVLQVHUWHG FHOOV '00,6,16 Read/write Address A5H Value after reset 0000H Recommended value 0002H. DMMISINS(15:0) holds the global MMISINS threshold for the PM data collection in downstream direction. A PM block with more than MMISINS misinserted cells is considered severely errored by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal MMISINS cells are misinserted the misinserted cell counters are incremented. 'RZQVWUHDP 0D[LPXP /RVW &/3 FHOOV '0/267 Read/write Address A6H Value after reset 0000H Recommended value 0003H. DMLOST0(15:0) holds the global MLOST0 threshold (CLP0 cells only) for the PM data collection in downstream direction. A PM block with more than MLOST0 lost cells is considered severely errored by the data collection algorithm. Accordingly the SECB counter is incremented. If less or equal MLOST0 cells are missing the lost cell counters are incremented. 'RZQVWUHDP 0D[LPXP (UURUV '0(55 Read/write Address A7H Value after reset 0000H Recommended value 0003H. DMERR(15:0) holds the global MERR threshold for the PM data collection in downstream direction. A BR cell carrying a block error result BLER value greater than MERR denotes a severely errored block. Accordingly the SECB counter is incremented. If BLER is less or equal MERR the BLER value is added to the error counter ERRC.
Data Sheet
3-72
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
6FDQ 5HJLVWHUV
The SCAN performs the OAM functions AIS, RDI and CC for all connections. It must be triggered by the microprocessor in 500 ms intervals. The SCAN procedure goes through all requested entries of the external connection memory, reads the data and writes back updated information. E.g. the SCAN checks if user cells has been received, increments counters and accordingly performs transitions in the AIS/RDI/CC state diagrams. Also AIS/RDI/CC cell insertion is done by the scan. The SCAN starts with the lower LCI bound programmed by the user and ends at the higher LCI bound. If for a connection a cell is to be inserted the SCAN halts the user cell stream for one cell cycle. The user cells are buffered intermediately (see ILJXUH 12). A SCAN cycle of one LCI lasts 32 clock cycles like a cell access. It uses idle times, i.e. it is initiated if no complete cell is available in the input UTOPIA buffer. Hence a certain number of idle cell cycles is needed by the SCAN to do its work. The idle cell cycles can be calculated from the difference between the sum of PHY payload rates and the maximum cell processing rate of the PXB 4340 AOP. 7DEOH shows some example values for SCAN period times as a function of PHY payload rates. It can be seen that 673 Mbit/s is the highest possible aggregate PHY payload rate if 16 K connections are used. 7DEOH 6&$1 SHULRGV IRU D FRUH FORFN RI 0+] 6XP RI 3+< SD\ORDG &HOO F\FOHV XVHG IRU &HOO F\FOHV DYDLODEOH 0LQLPXP 6&$1 UDWHV XVHU FHOOV IRU 6&$1 SHULRG IRU FRQQHFWLRQV 600 Mbit/s 1.415 Mcells/s 204 906 cycles/s 80 ms 625 Mbit/s 650 Mbit/s 673 Mbit/s 687 Mbit/s 1.474 Mcells/s 1.533 Mcells/s 1.587 Mcells/s 1.620 Mcells/s 145 943 cycles/s 86 981 cycles/s 32 768 cycles/s 0 112 ms 188 ms 500 ms not possible
The SCAN periods in 7DEOH are minimum values, as additional idle cycles occur if the PHYs user cell rate is below 100%. A typical link load value is <100%. The spare bandwidth is used for OAM cell insertion and microprocessor accesses to the external RAMs. While the SCAN mechanism processes the entries of all connections the DMA function can be activated. The read value of one specified Dword of each entry can be transferred to the microprocessor via a 32-entry DMA buffer. The occupied DMA buffer is signalled to the microprocessor via the MPDREQ pin. Also selected bits of the specified DMA entry can be overwritten during the DMA process, e.g. to clear state transition flags. With the Compressed DMA option a special Dword with a collection of state transition and status flags is transferred to the DMA buffer during the scan. This option allows to check the status of all connections rapidly. 1RWH 7KH 6&$1 UHJLVWHUV DUH ZULWH SURWHFWHG GXULQJ WKH 6&$1 PHFKDQLVP LV UXQQLQJ 6&67$76&$1B$&7
Data Sheet
3-73
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
'0$ :ULWH 5HJLVWHU ':'5/ Read/write Address B0H Value after reset 0000H DWDRL(15:8) DWDRL(7:0)
DWDRL(15:0)
DMA Write Register(15:0), specifies the lower 16-bit of the Dword to be written into the external connection RAM via DMA. The bit positions to be overwritten in the connection RAM Dword are specified with the associated mask register DMRL, the Dword of the RAM entry is selected by DCONF.INDEX.
'0$ :ULWH 5HJLVWHU ':'5+ Read/write Address B1H Value after reset 0000H SP DWDRH(7:0) DWDRH(14:8)
SP DWDRH(14:0)
Select Parity: if SP=0 the correct parity is generated when the dword is transferred to the external RAM; if SP=1 a false parity bit is generated. DMA Write Register(31:16), specifies the upper 16-bit of the Dword to be written into the external connection RAM via DMA. The bit positions to be overwritten in the connection RAM Dword are specified with the associated mask register DMRL, the Dword of the RAM entry is selected by DCONF.INDEX.
Data Sheet
3-74
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
'0$ 0DVN 5HJLVWHU '05/ Read/write Address B2H Value after reset 0000H DMRL(15:8) DMRL(7:0)
DMRL(15:0)
DMA Mask Register(15:0): 0 1 Bit is unchanged. Bit is replaced by corresponding DWDR-Bit, used for RMW operation on external RAM word selected by DCONF.INDEX.
'0$ 0DVN 5HJLVWHU +LJK '05+ Read/write Address B3H Value after reset 0000H DMRH(15:8) DMRH(7:0)
DMRH(15:0)
DMA Mask Register(31:16): 0 1 Bit is unchanged. Bit is replaced by corresponding DWDR-Bit, used for RMW operation on external RAM word selected by DCONF.INDEX.
Data Sheet
3-75
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
3+< (UURU ,QGLFDWLRQ 3+<(55/ Read/write Address B4H Value after reset 0000H PHYERRL(15:8) PHYERRL(7:0)
PHYERRL(15:0)
These bits have a one-to-one correspondence with the PHYs that are connected to the switch port. In case of an interruption of the physical transmission (e.g. laser failure) the microprocessor sets the respective PHYERR bit. The SCAN mechanism uses this indication together with the PHY number stored in each connection entry of the upstream external RAM (see VHFWLRQ ) to generate AIS cells. PHYERR bits are used in upstream direction only.
3+< (UURU ,QGLFDWLRQ 3+<(55+ Read/write Address B5H Value after reset 0000H Unused PHYERRL(23:16)
PHYERRH(23:16)
These bits have a one-to-one correspondence with the PHYs that are connected to the switch port. In case of an interruption of the physical transmission (e.g. laser failure) the microprocessor sets the respective PHYERR bit. The SCAN mechanism uses this indication together with the PHY number stored in each connection entry of the upstream external RAM (see VHFWLRQ ) to generate AIS cells. PHYERR bits are used in upstream direction only.
Data Sheet
3-76
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
'0$ 5HDG 5HJLVWHU '0$5 Read Address B6H Value after reset 0000H DMAR(15:8) DMAR(7:0)
DMAR(15:0)
DMA Read Register of DMA-FIFO (32 words deep). The external DMA controller has to be programmed to read this address.
1RWH 2XWSXW VHTXHQFH RI '0$ GDWD ELW IURP WKH H[WHUQDO 5$0 DUH DOZD\V RXWSXW DV FRQVHFXWLYH ELW ZRUGV %LWV DUH DOZD\V ORFDWHG LQ WKH ILUVW ZRUG LQ WKH VHFRQG ZRUG +HUHE\ ELW DOZD\V LQGLFDWHV WKH VRXUFH IURP GRZQVWUHDP 5$0 IURP 8SVWUHDP 5$0 '0$ &RQILJXUDWLRQ 5HJLVWHU '&21) Read/write Address B7H Value after reset 0000H Unused Unused DMAEN MODE INDEX(2:0)
Data Sheet
3-77
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
DMAEN
Enable MPDREQ output signal: 0 1 MPDREQ is always tristate and MPDACK is not evaluated. MPDREQ gets low impedance if DMA is requested, otherwise tristate. MPDREQ is MPDACK controlled. Standard DMA: 32 bit RMW operation on Dword of LCI entry selected with INDEX(2:0) using DWDR and DMR. Compressed DMA: 32 bit RMW operation on all interrupt relevant flags in LCI entry, no influence of DWDR, for bit mapping see VHFWLRQ 4.1.6.1.
MODE
Selects standard DMA or compressed DMA 0 1
INDEX(2:0)
Selects which word (0..7) in the LCI table is object of the RMW operation of standard DMA. INDEX is don't care in compressed mode (MODE=1).
7LPH &RQVWDQW 5HJLVWHU 6&&21) Read/write Address B8H Value after reset 0275H Unused MAXTR(3:0) CCDEFMAX(3:0) MAXTS(1:0)
MAXTS(1:0) MAXTR(3:0) CCDEFMAX(3:0)
Time for generation of CC cells if no user cell has arrived in the CC generation. Counted in multiples of SCAN cycles (typ. 500 ms). Time for transition from normal operation to LOC defect state in the CC evaluation. Counted in multiples of SCAN cycles (typ. 500 ms). Time for transition from LOC defect to LOC failure state in the CC evaluation. Counted in multiples of SCAN cycles (typ. 500 ms).
Data Sheet
3-78
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
7LPH &RQVWDQW 5HJLVWHU 6&&21) Read/write Address B9H Value after reset 0057H F4F5 PROP Unused IDLEMAX(2:0) ARDEFMAX(3:0) Unused
F4F5PROP
Control forced AIS/RDI cell generation (ARINS bit in external RAM) behaviour at F4TEP: 0 1 Generate 'F4RDI only' if ARINS is set. Generate 'F4RDI and F5AIS for all included VCCs if ARINS is set.
IDLEMAX(2:0)
Time for transition from AIS defect/failure to normal operation or from RDI defect/failure to normal operation. Counted in multiples of SCAN cycles. Time for transition from AIS defect to AIS failure state or RDI defect to RDI failure state. Counted in multiples of SCAN cycles.
ARDEFMAX(3:0)
1RWH 7KH W\SLFDO YDOXH IRU WKH 6&$1 F\FOH SHULRG LV PV 7LPH &RQVWDQW 5HJLVWHU 6&&21) Read/write Address BAH Value after reset 002DH SCPTOL(5:0) SCP(7:0) SCP(9:8)
Scan cycle tolerance: (maximum time - minimum time) for complete processing of 1 LCI counted in cell cycles). 1RWH 6&3 PXVW EH ! IRU 6&372/ XVDJH SCP(9:0) Scan cycle period: minimum time for processing of 1 LCI counted in cell cycles; necessary for equal distribution of OAM cells over 1 scan cycle, avoids OAM bursts generated by SCAN). 0
Data Sheet
SCPTOL(5:0)
Disables SCAN.
3-79 04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
6&$1 &RPPDQG 5HJLVWHU 6&&21) Read/write Address BBH Value after reset 0000H Unused Unused DMA DN OAM DN DMA UP OAM UP Unused START SC
DMAUP OAMUP DMADN OAMDN STARTSC
Select SCAN with DMA transfer upstream. Select SCAN with OAM processing upstream. Select SCAN with DMA transfer downstream. Select SCAN with OAM processing downstream. Start Scan up- and downstream with the selected processing. This bit is set by the microprocessor every 500 ms. As soon as the SCAN mechanism is started, this bit is reset to 0. The select bits can be defined with the same write access.
The select bits are modified only by the microprocessor. The SCAN start bit is set by the microprocessor and reset by the AOP immediately after the start of the SCAN. To determine the termination of the scan refer to the SCAN Status Register below. /RZHU %RXQGDU\ RI /&, 5DQJH 6&&21) Read/write Address BCH Value after reset 0000H Unused LCIMIN(7:0) LCIMIN(13:8)
LCIMIN(13:0)
Lower boundary of LCI range processed by SCAN (up- and downstream).
Data Sheet
3-80
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8SSHU %RXQGDU\ RI /&, 5DQJH 6&&21) Read/write Address BDH Value after reset 0000H Unused LCIMAX(7:0) LCIMAX(13:8)
LCIMAX(13:0)
Upper boundary of LCI range processed by SCAN (up- and downstream).
6&$1 6WDWXV 5HJLVWHU 6&67$7 Read only Address BEH Value after reset 0000H Unused Unused CGENP DMAD OAMD DTOG CGENP DMAD OAMD UTOG Unused SCAN ACT1
CGENP DMAD OAMD UTOG CGENP DMAD OAMD DTOG
Upstream cell generation pending, internal state for debugging. Upstream DMA done, internal state for debugging. Upstream OAM done, internal state for debugging. Upstream toggle flag, used for VP processing once in a SCAN cycle. Downstream Cell generation pending, internal state for debugging. Downstream DMA done, internal state for debugging. Downstream OAM done, internal state for debugging. Downstream toggle flag, used for VP processing once in a SCAN cycle.
SCAN mechanism was started and has not yet finished. SCANACT1 1RWH 7KH VFDQ ILQLVKHG FRQGLWLRQ LV 6&$1$&7 DQG 6&&2167$576&
Data Sheet
3-81
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
&XUUHQWO\ 3URFHVVHG /&, 6&67$7 Read only Address BFH Value after reset 8000H DE LCIS(7:0) DF LCIS(13:8)
DE DF LCIS(13:0)
DMA buffer empty = 0 words in FIFO. DMA buffer full 32 words in FIFO. Currently processed LCI up- and downstream. Internal state for debugging.
1RWH ,Q DSSOLFDWLRQV 6&$1 KDV WR EH VWDUWHG E\ WKH 3 HYHU\ PV WKH WLPHV JLYHQ KHUH DUH EDVHG RQ WKLV WLPLQJ ,Q WKH +: WKH VHWWLQJV DERYH UHSUHVHQW 1XPEHU RI 6&$1 F\FOHV )RU WHVW 6&$1 PD\ EH VWDUWHG LQ DUELWUDU\ WLPH SHULRGV ,QWHUUXSW DQG ,QWHUUXSW 0DVN 5HJLVWHUV
Interrupt bits signal unpredictable events to the controlling microprocessor, e.g. errors. Each interrupt bit signals a different event. Events which are associated to a certain connection, as e.g. the misinserted OAM cell interrupt are stored additionally also in the external connection RAM under the respective LCI entry. If one of these interrupt indications is set the corresponding error might have occured for at least one or more connections. Thus the microprocessor has to check all entries of the connection RAM dedicated to the respective direction for the indicated error. To clear interrupt bits the microprocessor must write a '1' to the respective bit. Writing a '0' has no effect. This behaviour simplifies interrupt management by separate interrupt routines. After a HW interrupt more than one interrupt bit might be set. Then each interrupt routine can clear the respective bit separately after having checked or corrected the interrupt cause.
Data Sheet
3-82
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
,QWHUUXSW 6WDWXV 5HJLVWHU ,65 Read/write Address D0H Value after reset 0000H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 UUPED DUPED UUSOCE DUSOCE UTOPIA parity error detected upstream. UTOPIA parity error detected downstream. UTOPIA start of cell or cell length error detected upstream. UTOPIA start of cell or cell length error detected downstream. UEDCER CRC-10 error detected in OAM cell in upstream direction. This error indication is also stored in Dword2, bit 13 in the upstream connection RAM entry of the respective LCI (see VHFWLRQ 3.9.1.3). DEDCER CRC-10 error detected in OAM cell in downstream direction. This error indication is also stored in Dword2, bit 13 in the downstream connection RAM entry of the respective LCI (see VHFWLRQ 3.9.3.3). RXCEL Indicates a non-empty receive buffer. It is cleared automatically after 27 read accesses of the RXRCEL register, i.e. after read-out of a complete cell. If further cells are in the receive buffer this bit is set again immediately. RXOV Indicates an overflow of the receive buffer; is set if at least one cell has been discarded due to a full receive cell buffer. OCIF Bit OCIF is set if * an OAM cell generated by the SCAN could not be inserted in downstream direction; * BR or FM cells could not be inserted in downstream direction; * "central control" loopback of LB cells could not be performed because insertion in downstream direction was not possible; * FM cells transformed to BR cells could not be inserted in downstream direction; This bit is the OR function result of all bits of CIFL and CIFH registers. 1RWH :ULWLQJ D WR ELW 2&,) ZLOO DOVR UHVHW UHJLVWHUV &,)/ DQG &,)+ Is set if an OAM cell generated by the SCAN could not be inserted in upstream direction. This occurs if during the insertion window defined in register SCCONF2 the upstream internal 32-cell buffer filling was constantly beyond the insertion threshold defined in register OAMTHRU. DUTBO UTOPIA Transmit-Buffer Overflow downstream.
Bit 10
Bit 9
Bit 8 Bit 7
Bit 6
Bit 5
Data Sheet
3-83
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 4 (Bit 3..0)
Bit 3
Bit 2
Bit 1
Bit 0
DBERR DMA Buffer Overflow or Underflow. These bits indicate important transitions of AIS, RDI or CC state diagrams (see )LJXUHV 17, 18 and 22) for any connection with the respective functionality enabled. These are collection interrupts of the respective connection specific flags in the external RAM: DCSTTR Downstream VC-related state transition occurred, i.e. one of the bits 14..19 of Dword2 in downstream external RAM entry set (see VHFWLRQ 3.9.3.3). UCSTTR Upstream VC-related state transition occurred, i.e. one of the bits 14..19 of Dword2 in upstream external RAM set (see VHFWLRQ 3.9.1.3). DPSTTR Downstream VP-related state transition occurred, i.e. one of the bits 22..27 of Dword4 in downstream external RAM set (see VHFWLRQ 3.9.4.1). UPSTTR Upstream VP-related state transition occurred, i.e. one of the bits 22..27 of Dword4 in upstream external RAM set (see VHFWLRQ 3.9.2.1).
,QWHUUXSW 6WDWXV 5HJLVWHU ,65 Read/write Address D1H Value after reset 0000H Bit 15:9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Unused SCTOUT Time-out for Scan processing within SCP. Upstream Loopback cell discarded. Downstream Loopback cell discarded. Cell received for an invalid connection (VCON=0) upstream. VCON is bit19 in Dword0 of upstream RAM (see VHFWLRQ 3.9.1.1). Cell received for an invalid connection (VCON=0) downstream. VCON is bit19 in Dword0 of downstream RAM (see VHFWLRQ 3.9.3.1). RAM-Parity error occurred upstream. RAM-Parity error occurred downstream. UOAMIS Mis-inserted OAM cell detected upstream. This indication is also stored per connection in bit 12 of Dword2 in the upstream external RAM. Mis-inserted OAM cell detected downstream. This indication is also stored per connection in bit 12 of Dword2 in the downstream external RAM.
Bit 0
DOAMIS
Data Sheet
3-84
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
,QWHUUXSW 0DVN 5HJLVWHU ,05 Read/write Address D2H Value after reset 0000H IMR0(15:8) IMR0(7:0)
IMR0(15:0)
Interrupt mask register for ISR0: 0 1 Setting of corresponding bit in ISR0 does not activate the interrupt pin MPINT. Setting of corresponding bit in ISR0 activates MPINT.
,QWHUUXSW 0DVN 5HJLVWHU ,05 Read/write Address D3H Value after reset 0000H Unused IMR1(7:0) IMR1(8)
IMR1(8:0)
Interrupt mask register for ISR1: 0 1 Setting of corresponding bit in ISR1 does not activate the interrupt pin MPINT. Setting of corresponding bit in ISR1 activates MPINT.
/RZ
&HOO ,QVHUWLRQ )DXOW 5HJLVWHU ORZ DQG KLJK &,)/ DQG &,)+
Read Address D4H Value after reset 0000H CIF(15:8) CIF(7:0)
Data Sheet
3-85
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
+LJK Read Address D5H Value after reset 0000H Unused CIF(23:16)
CIF(23:0)
For the respective Port 15..0 in downstream direction an OAM cell could not be inserted. This occurs during the SCAN process if between consecutive LCIs there is no opportunity to insert the required OAM cell. OAM cells are not inserted if the filling level of the respective qeue exceeds the threshold specified in the OAMTHRD register. The indication may also be generated for any of the following reasons: * BR or FM cells could not be inserted in downstream direction; * "central control" loopback of LB cells could not be performed because insertion in downstream direction was not possible; * FM cells transformed to BR cells could not be inserted in downstream direction; Bit OCIF in register ISR0 is the OR function result of all bits of CIFL and CIFH registers. 1RWH :ULWLQJ D WR ELW 2&,) LQ UHJLVWHU ,65 ZLOO DOVR UHVHW UHJLVWHUV &,)/ DQG &,)+
Data Sheet
3-86
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8723,$ ,QWHUIDFH 5HJLVWHUV
8723,$ &RQILJXUDWLRQ 5HJLVWHU 87&21) Read/write Address E0H Value after reset 0000H This register configures the ATM side UTOPIA interfaces. Unused Unused UTA16 UTAPAR Unused UTACONF(1:0)
Bit (15:5) UTA16
Unused Select 8- or 16-bit UTOPIA Data bus 0 1 8 bit data bus at ATM side. 16 bit data bus at ATM side. Don't check parity of ATM receive data. Check parity of ATM receive data.
UTAPAR
Enables/disables parity check 0 1
Bit (2) UTACONF(1:0)
Unused Configuration of mode at ATM side : 00 01 10 11 4 x 6 port 3 x 8 port 2 x 12 port UTOPIA Level 1 (4 x 1 port)
Data Sheet
3-87
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8723,$ &RQILJXUDWLRQ 5HJLVWHU 87&21) Read/write Address E1H Value after reset 0000H This register configures the PHY side UTOPIA interfaces and the defines the LCI location. Unused Unused UTP16 Unused UTPPAR LCIMOD(1:0) UTPCONF(1:0)
Bit(15:10) LCIMOD(1:0)
Unused Position of LCI up/downstream: 00 01 10 11 LCI(13:12) = UDF(7:6), LCI(11:0) = VPI(11:0) LCI(13:12) = 00, LCI(11:0) = VPI In this mode no ICC possible. LCI(13:0) = VCI(13:0) F4-OAM/User-Flow not supported. Is not allowed, will be handled as '10'.
Bit(7:5) UTP16
Unused Select 8- or 16-bit UTOPIA Data bus 0 1 8 bit data bus at PHY side. 16 bit data bus at PHY side.
Bit(3) UTPPAR
Unused Enables/disables parity check 0 1 Don't check parity of PHY receive data. Check parity of PHY receive data. 4 x 6 port 3 x 8 port 2 x 12 port UTOPIA Level 1 (4 x 1 port)
UTPCONF(1:0)
Configuration of mode at PHY side : 00 01 10 11
Data Sheet
3-88
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
/RZ
8SVWUHDP 3RUW (QDEOH ORZ DQG KLJK 8357(1/ DQG 8357(1+
Read/write Address E2H Value after reset 0000H UPORTEN(15:8) UPORTEN(7:0)
+LJK Read/write Address E3H Value after reset 0000H Unused UPRTEN(23:16)
Bit(15:8) UPRTEN(23:16)
Unused 0 1 Disables UTOPIA port upstream. Enables UTOPIA port upstream.
/RZ
'RZQVWUHDP 3RUW (QDEOH ORZ DQG KLJK '357(1/ DQG '357(1+
Read/write Address E4H Value after reset 0000H DPRTEN(15:8) DPRTEN(7:0)
Data Sheet
3-89
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
+LJK Read/write Address E5H Value after reset 0000H Unused DPRTEN(23:16)
Bit(15:0) DPRTEN(23:0)
Unused 0 1
in High word only Disables UTOPIA port downstream. Enables UTOPIA port downstream.
2$0 &HOO ,QVHUWLRQ 7KUHVKROG 8SVWUHDP 2$07+58 Read/write Address E6H Value after reset 001EH Unused Unused OAMTHRU(5:0)
OAMTHRU(5:0)
Threshold for forced OAM cell insertion in upstream direction. If the upstream 32-cell buffer is filled beyond this level OAM cells are inserted with lower priority than user cells. Recommended value 30 (1EH). 0 1..31 >31 OAM cell insertion upstream only possible if no cell from UTOPIA is received. Cell insertion has higher priority until filling level of upstream 32-cell buffer reaches this threshold. OAM cells are always inserted with higher priority (in case of 32-cell buffer overflow backpressure to PHY).
Data Sheet
3-90
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
2$0 &HOO ,QVHUWLRQ 7KUHVKROG 'RZQVWUHDP 2$07+5' Read/write Address E7H Value after reset 0060H Unused Unused OAMTHRD(6:0)
OAMTHRD(6:0)
Threshold for forced OAM cell insertion in downstream direction. If a queue of the downstream shared buffer is filled beyond this level OAM cells destined to the respective PHY are not inserted. 0 1...95 >95 No cell insertion downstream possible. Cell insertion is possible until queue filling level reaches threshold. Cell insertion downstream only limited by buffer overflow condition.
%DFNSUHVVXUH 7KUHVKROG 'RZQVWUHDP %37+5' Read/write Address E8H Value after reset 0060H Unused Unused BPTHRD(6:0)
BPTHRD(6:0)
Queue backpressure level in downstream direction. If a queue exceeds this threshold the downstream receive UTOPIA interface does not accept any more cell: 0 1...95 Always backpressure to downstream receive UTOPIA interface for all ports. Backpressure to the respective PHY of the downstream receive UTOPIA interface if queue filling level reaches threshold. Queue specific backpressure disabled, backpressure controlled by shared buffer overflow only.
>95
(Recommended value is 65.)
Data Sheet
3-91
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
0LVFHOODQHRXV 5HJLVWHUV
5$0 7\SH 6HOHFW 5HJLVWHU 0,6& Read/write Address F0H Value after reset 0000H Unused Unused RAMSEL(1:0) SWRES
RAMSEL(1:0)
Selects the type of RAM used for upstream and downstream external connection RAM. 00 01 1 Mbit external RAM. 2 Mbit external RAM.
SWRES
SW-reset. If set to one the internal reset cycle is executed.
7HVW 5HJLVWHU 7(675 Read/write Address F1H Value after reset 0000H Unused Unused TINT LOOPUD LOOPDU
Data Sheet
3-92
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Unused(15:3) TINT Test of Interrupt. 0 1 Normal operation, test of interrupts is disabled. Interrupt generation test mode: Normal interrupt generation is disabled; interrupt test procedure is controlled by consecutive write accesses to register RXRCEL (offset address: 9DH): will set bit ISR0(0) will set bit ISR0(1) ... will 127 set bit ISR0(9) 1RWH 7KLV LQWHUUXSW VWDWXV ELW LV DQ H[FHSWLRQ DQG FDQQRW EH WHVWHG E\ WKLV SURFHGXUH will set bit ISR0(10) ... will set bit ISR0(15) will set bit ISR1(0) ... will set bit ISR1(15)
1. write: 2. write: ... 10. write:
11. write: ... 16. write: 17. write: ... 32. write: LOOPUD 1 LOOPDU 1
Bit TINT has to be set to '0' to re-enter normal operation. Enable testloop up-to-downstream. Enable testloop down-to-upstream.
7HVW 5HJLVWHU 7(675 Read/write Address F2H Value after reset 0000H Reserved for device test only. Don't write.
Data Sheet
3-93
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
/RZ
9HUVLRQ 5HJLVWHU ORZ DQG KLJK 9(5/ DQG 9(5+
Read Address F3H Value after reset A06DH +LJK Read Address F4H Value after reset 523BH VERH 1RWH 7KHVH DUH WKH ,'ELWV RI WKH ERXQGDU\ VFDQ VHTXHQFH VERL
01010010001110111010000001101101
Data Sheet
3-94
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
%,67 0RGH 5HJLVWHU /RZ %,670/ Read/write Address F5H Value after reset 0000H RXR UTTXD1 UTRXD UTTXU UTRXU NCP UTTXD3 UTTXD2
Bit coding(1:0)
Selects the BIST function. 00 01 10 11 BIST inactive, normal operation mode. Test of BIST circuit. Start BIST. Diagnose mode (not used).
RXR NCP UTTXD1..3 UTRXD UTTXU UTRXU
Select BIST function for Receive Buffer Select BIST function for Cell Processing RAM Select BIST function for UTOPIA Downstream Transmit (shared) Buffer 1..3 Select BIST function for UTOPIA Downstream Receive Buffer Select BIST function for UTOPIA Upstream Transmit Buffer Select BIST function for UTOPIA Upstream Receive Buffer
%,67 0RGH 5HJLVWHU +LJK %,670+ Read/write Address F6H Value after reset 0000H PMDC6 PMDC2 PMDC1 PMDC0 PMAIN PMDC5 PMDC4 PMDC3
Data Sheet
3-95
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit coding(1:0)
Selects the BIST function. 00 01 10 11 BIST inactive, normal operation mode. Test of BIST circuit. Start BIST. Diagnosis mode (not used).
PMDC6..0 PMAIN
Select BIST function for PM data collection RAM part 6..0 Select BIST function for PM main RAM
%,67 'RQH 5HJLVWHU %,67'1 Read Address F7H Value after reset 0000H The 16 bits of this register have a one-to-one correspondence with internal RAM blocks. These bits are set by the AOP if the respective BIST is completed. All bits are reset by any write to the BISTERR register. After completion of a BIST the AOP must be reset. Bit 15..9 Bit 8 Bit 7 Bit 6 Bit 5..3 Bit 2 Bit 1 Bit 0 BIST of PMDC6..0 RAM block is completed BIST of PMAIN RAM is completed BIST of RXR Buffer is completed BIST of NCP RAM is completed BIST of UTOPIA Downstream RAM block 3..1 is completed BIST of UTOPIA Downstream Receive Buffer is completed BIST of UTOPIA Upstream Transmit Buffer is completed BIST of UTOPIA Receive Upstream Buffer is completed
Data Sheet
3-96
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
%,67 (UURU 5HJLVWHU %,67(55 Read Address F8H Value after reset 0000H The 16 bits of this register have a one-to-one correspondence with internal RAM blocks. These bits are set if during BIST execution an error occured in the respective RAM block. Bit 15..9 Bit 8 Bit 7 Bit 6 Bit 5..3 Bit 2 Bit 1 Bit 0 BIST of PMDC6..0 RAM block is faulty BIST of PMAIN RAM is faulty BIST of RXR Buffer is faulty BIST of NCP RAM is faulty BIST of UTOPIA Downstream RAM block 3..1 is faulty BIST of UTOPIA Downstream Receive Buffer is faulty BIST of UTOPIA Upstream Transmit Buffer is faulty BIST of UTOPIA Receive Upstream Buffer is faulty
Data Sheet
3-97
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Dword
([WHUQDO DQG ,QWHUQDO 5$0 8SVWUHDP ([WHUQDO 5$0 ) (QWU\ 'ZRUGV
CEDCID(6:0) CTSDCID(6:0) 30..15
CSDCID(6:0) 19 18 17 16 15 14 13 12
CPMTID(6:0) 11..7 CPMOID(6:0) 654 3..0 PN(4:0)
3 31 30 29 28 2 31 1 31
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCI2(13:0)
0 31 30 29 28 27 26 25 24 23 22 21 20 19 8SVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31
PAR Dword parity protection. In normal operation write to 0. Should always read as 0. CPMTEN Enable a Terminating F5 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier CPMTID in Dword3. CPMOEN Enable an Originating F5 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier CPMOID in Dword3. CLBS F5 Loopback State according to I.610. Should be set before inserting a LB cell, cleared after reception of the looped cell. CSRCIDEN Loopback of F5 LB cells using LB source ID 1 Enabled. Normally this bit is =0 as the location ID is used to detect intra-domain LB cells.
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
CLOCIDEN Loopback of F5 LB cells using LB location ID 1 Enabled. Normally this bit is =1 as according to the standard the location ID is used to detect intra-domain LB cells
Bit 25
ACDEAC Treatment of Activation/Deactivation cells at their destination points: 0 1 Discard (if Activation/ Deactivation function is not used) Extract to receive buffer (if Activation/ Deactivation is supported)
3-98 04.2000
Data Sheet
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 24
DISF5 0 1 Enable F5 processing, default. Disable F5 processing. All F5 OAM cells are discarded. No F5 Terminating Segment Point. F5 Terminating Segment Point. Do not adjust at F5 OEP. No F5 Originating Segment Point. F5 Originating Segment Point.
Bit 23
CTSP 0 1
Bit 22
COSP 0 1
Bit 21 Bit 20
Unused It is recommended to initialize with '0'. CIP 0 1 F5 Originating End Point (OEP). F5 Intermediate Point. Connection not activated, cells for this LCI are discarded. Connection activated.
Bit 19
VCON 0 1
LCI2(13:0)18..5
Pointer to the VP connection data of the actual VCC. F4 pointer in ILJXUH . Meaning of bits 18..5 depends on bit field 'lcimod' in register UTCONF1. PHY Number associated with this LCI. Used for PHY specific AIS generation (see P register PHYERR).
PN(4:0)4..0
Data Sheet
3-99
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8SVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Initialize to 0 at connection setup. Do not change by P in normal operation. CICCEN 1 Bit 13 CSCCTEN 1 Bit 12 Bit 11 Terminate a F5 Segment Continuity Check. Should only be enabled at a F5 TSP (CTSP=1). Enable Internal Continuity Check, originating ICC in upstream direction. Set to 0 if ICC is not used.
Bit 30..15 Bit 14
Reserved, set to 0. CSCCOEN 1 Originate a F5 Segment Continuity Check Flow. Should only be enabled at a F5 OSP (COSP=1). Originate a F5 End-to-End Continuity Check Flow. Should only be enabled at a F5 OEP (CIP=0). F5 RDI monitoring disabled. F5 RDI monitoring enabled. State transition to RDI failure state and out of RDI failure state is reported by use of the P interrupt UCSTTR. F5 AIS monitoring disabled. F5 AIS monitoring enabled. State transition to AIS failure state and out of AIS failure state is reported by use of the P interrupt UCSTTR. F5 CC monitoring disabled. F5 CC monitoring enabled. State transition to LOC failure state and out of LOC failure state is reported by use of the P interrupt UCSTTR.
Bit 10
CECCOEN 1
Bit 9
CRDIMEN 0 1
Bit 8
CAISMEN 0 1
Bit 7
CCCMEN 0 1
Data Sheet
3-100
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 6
CARIEN 0 1 F5 AIS Cell insertion disabled. F5 AIS Cell insertion enabled. Independent on the reason for cell generation (forced insertion by ARINS, physical error by P register PHYERR, detected LOC or AIS state) AIS/RDI cell generation is always controlled by this flag. Used e.g. to suppress RDI at endpoints of multicast connections.
Bit 5
CLOCFAI F5 LOC failure state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. CLOCDEF F5 LOC defect state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. CRDIFAI F5 RDI failure state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. CRDIDEF F5 RDI defect state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. CAISFAI F5 AIS failure state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. CAISDEF F5 AIS defect state indication. Initialize to 0 at connection setup. Do not change by P in normal operation.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Sheet
3-101
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8SVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Unused It is recommended to initialize with '0'. Identifier for Data Collection on terminated / intermediate Segment F5 BR cells. Related enable CTSDCEN in Dword3. CLOCF2N 1 Indication for a state transition from F5 LOC failure state to F5 LOC normal state. Set by AOP, must be cleared by the P. Reported with interrupt UCSTTR if enabled with CCCMEN=1 (Dword1). Indication for a state transition from F5 LOC defect state to F5 LOC failure state. Set by AOP, must be cleared by the P. Reported with interrupt UCSTTR if enabled with CCCMEN=1 (Dword1). Indication for a state transition from F5 RDI failure state to F5 RDI normal state. Set by AOP, must be cleared by the P. Reported with interrupt UCSTTR if enabled with CRDIMEN=1 (Dword1). Indication for a state transition from F5 RDI defect state to F5 RDI failure state. Set by AOP, must be cleared by the P. Reported with interrupt UCSTTR if enabled with CRDIMEN=1 (Dword1). Indication for a state transition from F5 AIS failure state to F5 AIS normal state. Set by AOP, must be cleared by the P. Reported with interrupt UCSTTR if enabled with CAISMEN=1 (Dword1). Indication for a state transition from F5 AIS defect state to F5 AIS failure state. Set by AOP, must be cleared by the P. Reported with interrupt UCSTTR if enabled with CAISMEN=1 (Dword1).
30..27 CTSDCID(6:0) Bit 19
Bit 18
CLOCD2F 1
Bit 17
CRDIF2N 1
Bit 16
CRDID2F 1
Bit 15
CAISF2N 1
Bit 14
CAISD2F 1
Data Sheet
3-102
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 13
EDCERR 1 Wrong EDC (CRC10) in an OAM cell detected on this connection. Reported with interrupt UEDCER. Mis-inserted OAM cell discarded on this connection. Reported with interrupt UOAMIS.
Bit 12
OAMMIS 1
Bit 11..7 Bit 6
Initialize to 0 at connection setup. Do not change by P in normal operation. CCCINS 0 1 Default; normal CC cell insertion Force insertion of F5 CC Cells for all activated CC flows; period determined by MAXTS in register SCCONF1.
Bit 5 Bit 4
Initialize to 0 at connection setup. Do not change by P in normal operation. CARINS: 1 Force insertion of F5 AIS Cells upstream. Cells are generated with every 2nd SCAN. Used e.g. for AIS insertion due to VCC performance degrade (determined by PM function).
Bit 3..0
Initialize to 0 at connection setup. Do not change by P in normal operation.
Data Sheet
3-103
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8SVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. CEDCEN Enable Data Collection on F5 End-to-End BR cells. Related identifier CEDCID. CSDCEN Enable Data Collection on F5 Segment BR cells directly generated from F5 segment FM cells. Related identifier CSDCID. CTSDCEN Enable Data Collection on terminated / intermediate F5 Segment BR cells, related identifier CTSPMDCID is in Dword2. Identifier for Data Collection on F5 End-to-End BR cells. Related enable CEDCEN. Identifier for Data Collection on F5 Segment BR cells directly generated from F5 segment FM cells. Related enable CSDCEN. Identifier for a terminating F5 Segment or End-to-End FM flow. Related enable CPMTEN in Dword0. Identifier for an originating F5 Segment or End-to-End FM flow. Related enable CPMOEN in Dword0.
Bit 30
Bit 29
Bit 28
CEDCID(6:0) CSDCID(6:0) CPMTID(6:0) CPMOID(6:0)
Dword
8SVWUHDP ([WHUQDO 5$0 ) (QWU\ 'ZRUGV
PEDCID(6:0) 30..15
PSDCID(6:0) 13 PPMTID(6:0) 12..9
PTSDCID(6:0) PPMOID(6:0) 4..0
7 31 6 31 30 29 28 5 31
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8765
4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Data Sheet
3-104
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8SVWUHDP ) 2$0 HQWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. PPMTEN Enable a terminating F4 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier PPMTID in Dword6. PPMOEN Enable an originating F4 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier PPMOID in Dword6. Initialize to 0 at a connection setup. Do not change by P in normal operation. PLOCF2N 1 Indication for a state transition from LOC failure state to LOC normal state. Set by AOP, must be cleared by the P. Reported with interrupt UPSTTR if enabled with PCCMEN=1 in Dword5. Indication for a state transition from LOC defect to LOC failure state. Set by AOP, must be cleared by the P. Reported with interrupt UPSTTR if enabled with PCCMEN=1 in Dword5. Indication for a state transition from AIS failure to AIS normal state. Set by AOP, must be cleared by the P. Reported with interrupt UPSTTR if enabled with PRDIMEN=1 in Dword5. Indication for a state transition from AIS defect to AIS failure state. Set by AOP, must be cleared by the P. Reported with interrupt UPSTTR if enabled with PRDIMEN=1 in Dword5. Indication for a state transition from AIS failure to AIS normal state. Set by AOP, must be cleared by the P. Reported with interrupt UPSTTR if enabled with PAISMEN=1 in Dword5.
Bit 30
Bit 29
Bit 28 Bit 27
Bit 26
PLOCD2F 1
Bit 25
PRDIF2N 1
Bit 24
PRDID2F 1
Bit 23
PAISF2N 1
Data Sheet
3-105
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 22
PAISD2F 1 Indication for a state transition from AIS defect to AIS failure state. Set by AOP, must be cleared by the P. Reported with interrupt UPSTTR if enabled with PAISMEN=1 in Dword5.
Bit 21
PLBS F4 Loopback State according to I.610. Should be set before inserting a LB cell, cleared after reception of the looped cell. VPCCHK VPCI consistency check. If set indicates that a LB cell has been looped. PSRCIDEN Loopback of F4 LB Cells using LB source ID 1 Enabled. Normally this bit is =0 as the location ID is used to detect intra-domain LB cells.
Bit 20 Bit 19
Bit 18
PLOCIDEN Loopback of F4 LB Cells using LB location ID 1 Enabled. Normally this bit is =1 as according to the standard the location ID is used to detect intra-domain LB cells. Enable F4 processing, default. Disable F4 processing. All F4 OAM cells are discarded. Option selected e.g. at AAL interworking point. No F4 Terminating Segment Point. F4 Terminating Segment Point. No F4 Originating Segment Point. F4 Originating Segment Point. Do not adjust at F4 TEP. F4 Terminating End Point (TEP). F4 intermediate Point.
Bit 17
DISF4 0 1
Bit 16
PTSP 0 1
Bit 15
POSP 0 1
Bit 13
PIP 0 1
Bit 12..9 Bit 8
Initialize to 0 at connection setup. Do not change by P in normal operation. PCCINS 1 Force insertion of F4 CC Cells for all activated CC flows; period determined by MAXTS in register SCCONF1.
Data Sheet
3-106
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 7 Bit 6
Initialize to 0 at connection setup. Do not change by P in normal operation. PARINS 1 Force insertion of F4 AIS Cells upstream. Used e.g. for AIS insertion due to VPC performance degrade (determined by PM function).
Bit 5 Bit 4..0
Initialize to 1 at connection setup. Do not change by P in normal operation. Initialize to 0 at connection setup. Do not change by P in normal operation.
8SVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Initialize to 0 at connection setup. Do not change by P in normal operation. PICCEN 1 Bit 13 PSCCTEN 1 Bit 12 PECCTEN 1 Bit 11 PSCCOEN 1 Bit 10 Bit 9 Originate a F4 Segment Continuity Check. Should only be enabled at a F4 OSP (POSP=1). Terminate a F4 End-to-End Continuity Check. Should only be enabled at a F4 TEP (PIP=0). Terminate a F4 Segment Continuity Check. Should only be enabled at a F4 TSP (PTSP=0). Enable Internal Continuity check, in upstream direction originating ICC is enabled.
Bit 30..15 Bit 14
Reserved, set to 0. PRDIMEN 0 1 F4 RDI monitoring disabled. F4 RDI monitoring enabled. State transition to RDI failure state and out of RDI failure state is reported by use of the interrupt UPSTTR.
Data Sheet
3-107
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 8
PAISMEN 0 1 F4 AIS monitoring disabled. F4 AIS monitoring enabled. State transition to AIS-failure state and out of AIS-failure state is reported by use of the P interrupt UPSTTR. F4 CC monitoring disabled. F4 CC monitoring enabled. State transition to LOC failure state and out of LOC failure state is reported by use of the P interrupt UPSTTR. F4 AIS/RDI Cell insertion disabled. F4 AIS/RDI Cell insertion enabled. Independent of the reason for cell generation (forced insertion by ARINS, physical error by P register PHYERR, detected LOC or AIS state) AIS/RDI cell generation is always enabled with this flag. Used e.g. to suppress RDI at endpoints of multicast connections. F4 LOC failure state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. F4 LOC defect state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. F4 RDI failure state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. F4 RDI defect state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. F4 AIS failure state indication. Initialize to 0 at connection setup. Do not change by P in normal operation. F4 AIS defect state indication. Initialize to 0 at connection setup. Do not change by P in normal operation.
Bit 7
PCCMEN 0 1
Bit 6
PARIEN 0 1
Bit 5
PLOCFAI 1
Bit 4
PLOCDEF 1
Bit 3
PRDIFAI 1
Bit 2
PRDIDEF 1
Bit 1
PAISFAI 1
Bit 0
PAISDEF 1
Data Sheet
3-108
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
8SVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. PEDCEN Enable Data Collection on F4 End-to-End BR cells. Related identifier PEDCID. PSDCEN Enable Data Collection on F4 Segment BR cells directly generated from F4 Segment FM cells. Related identifier PSDCID. PTSDCEN Enable Data Collection on terminated / intermediate F4 Segment BR cells, related identifier PTSDCID in Dword7. Identifier for Data Collection on F4 End-to-End BR cells. Related enable PEDCEN. Identifier for Data Collection on F4 Segment BR cells directly generated from F4 Segment FM cells. Related enable PSDCEN. Identifier for a terminating F4 Segment or End-to-End FM flow. Related enable PPMTEN in Dword4. Identifier for an originating F4 Segment or End-to-End FM flow. Related enable PPMOEN in Dword4.
Bit 30
Bit 29
Bit 28
PEDCID(6:0) PSDCID(6:0) PPMTID(6:0) PPMOID(6:0)
8SVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Unused It is recommended to initialize with '0'. Identifier for Data Collection on terminated / intermediate F4 Segment BR cells. Related enable PTSDCEN in Dword6.
Bit 30..7 PTSDCID(6:0)
Data Sheet
3-109
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Dword
'RZQVWUHDP ([WHUQDO 5$0 ) (QWU\ 'ZRUGV
CEDCID(6:0) CTSDCID(6:0) 30..15 20 19 CSDCID(6:0)
CPMTID(6:0) 11..7 CPMOID(6:0) 654 3..0 PN(4:0) 19 18 17 16 15 14 13 12
3 31 30 29 28 2 31 1 31
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCI2(13:0)
0 31 30 29 28 27 26 25 24 23 22
'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. CPMTEN Enable a Terminating F5 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier CPMTID in Dword3. CPMOEN Enable an Originating F5 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier CPMOID in Dword3. CLBS F5 Loopback State according to I.610. Should be set before inserting a LB cell, cleared after reception of the looped cell. CSRCIDEN Loopback of LB cells using LB source ID 1 Bit 26 Enabled. Normally this bit is =0 as the location ID is used to detect intra-domain LB cells.
Bit 30
Bit 29
Bit 28
Bit 27
CLOCIDEN Loopback of LB cells using LB location ID 1 Enabled. Normally this bit is =1 as according to the standard the location ID is used to detect intra-domain LB cells.
Bit 25
ACDEAC Treatment of Activation/Deactivation cells at their destination points: 0 1 Discard (if Activation / Deactivation function is not used) Extract to receive buffer (if Activation / Deactivation is supported)
Data Sheet
3-110
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 24
DISF5 0 1 Enable F5 processing, default. Disable F5 processing. All F5 OAM cells are discarded. No F5 Terminating Segment Point. F5 Terminating Segment Point. No F5 Originating Segment Point. F5 Originating Segment Point. Do not adjust at F5 TEP. F5 Terminating End Point (TEP). F5 Intermediate Point. Connection not activated, cells for this LCI are discarded. Connection activated.
Bit 23
CTSP 0 1
Bit 22
COS 0 1
Bit 20
CIP 0 1
Bit 19
VCON 0 1
LCI2(13:0)
Pointer to the VP connection data of the actual VCC. F4 pointer in ILJXUH ). Meaning of bits 18..5 depends on bit field 'lcimod' in register UTCONF1. PHY Number associated with this LCI. Used for PHY specific RDI cell generation.
PN(4:0)
Data Sheet
3-111
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Initialize to 0 at connection setup. Do not change by P in normal operation. CICCEN 1 Bit 13 CSCCTEN 1 Bit 12 CECCTEN 1 Bit 11 CSCCOEN 1 Bit 10 Bit 9 Originate a F5 Segment Continuity Check Flow. Should only be enabled at a F5 OSP (COSP=1). Terminate a F5 End-to-End Continuity Check Flow. Should only be enabled at a F5 TEP (CIP=0). Terminate a F5 Segment Continuity Check. Should only be enabled at a F5 TSP (CTSP=1). Enable Internal Continuity Check, terminating ICC in downstream direction. Set to 0 if ICC is not used.
Bit 30..15 Bit 14
Reserved, set to 0. CRDIMEN 0 1 F5 RDI monitoring disabled. F5 RDI monitoring enabled. State transition to ASI failure state and out of ASI failure state is reported by use of the P interrupt DCSTTR. F5 AIS monitoring disabled. F5 AIS monitoring enabled. State transition to AIS failure state and out of AIS failure state is reported by use of the P interrupt DCSTTR.
Bit 8
CAISMEN 0 1
Data Sheet
3-112
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 7
CCCMEN 0 1 F5 CC monitoring disabled. F5 CC monitoring enabled. State transition to LOC failure state and out of LOC failure state is reported by use of the P interrupt DCSTTR. F5 AIS or RDI Cell insertion disabled. F5 AIS or RDI Cell insertion enabled. Independent of the reason for cell generation (forced insertion by ARINS, detected LOC or AIS state) AIS/RDI cell generation is always controlled by this flag. Necessary e.g. to suppress RDI at endpoints of multicast or unidirectional connections.
Bit 6
CARIEN 0 1
Bit 5
CLOCFAI F5 LOC failure state. Initialize to 0 at connection setup. Do not change by P in normal operation. CLOCDEF F5 LOC defect state. Initialize to 0 at connection setup. Do not change by P in normal operation. CRDIFAI F5 RDI failure state. Initialize to 0 at connection setup. Do not change by P in normal operation. CRDIDEF F5 RDI defect state. Initialize to 0 at connection setup. Do not change by P in normal operation. CAISFAI F5 AIS failure state. Initialize to 0 at connection setup. Do not change by P in normal operation. CAISDEF F5 AIS defect state. Initialize to 0 at connection setup. Do not change by P in normal operation.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data Sheet
3-113
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Identifier for Data Collection on terminated / intermediate F5 Segment BR cells. Related enable is CTSDCEN in Dword3. CLOCF2N 1 Indication for a state transition from F5 LOC failure state to F5 LOC normal state. Set by AOP, reset by the P. Reported with interrupt DCSTTR if enabled with CAISMEN=1 (Dword1). Indication for a state transition from F5 LOC defect state to F5 LOC failure state. Set by AOP, reset by the P. Reported with interrupt DCSTTR if enabled with CCCMEN=1 (Dword1). Indication for a state transition from F5 RDI failure state to F5 RDI normal state. Set by AOP, reset by the P. Reported with interrupt DCSTTR if enabled with CRDIMEN (Dword1). Indication for a state transition from F5 RDI defect state to F5 RDI failure state. Set by AOP, reset by the P. Reported with interrupt DCSTTR if enabled with CRDIMEN=1. (Dword1. Indication for a state transition from F5 AIS failure state to F5 AIS normal state. Set by AOP, reset by the P.Reported with interrupt DCSTTR if enabled with CAISMEN=1 (Dword1). Indication for a state transition from F5 AIS defect state to F5 AIS failure state. Set by AOP, reset by the P. Reported with interrupt DCSTR if enabled with CAISMEN=1 (Dword1). Wrong EDC (CRC10) in an OAM cell detected. Reported with interrupt DEDCER.
CTSDCID(6:0) Bit 19
Bit 18
CLOCD2F 1
Bit 17
CRDIF2N 1
Bit 16
CRDID2F 1
Bit 15
CAISF2N 1
Bit 14
CAISD2F 1
Bit 13
EDCERR 1
Data Sheet
3-114
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 12
OAMMIS 1 Miss inserted OAM cell discarded. Reported with interrupt DOAMIS.
Bit 11..7 Bit 6
Initialize to 0 at connection setup. Do not change by P in normal operation. CCCINS 0 1 Default, normal CC cell insertion. Force insertion of F5 CC Cells for all activated CC flows; period determined by MAXTS in register SCCONF1.
Bit 5 Bit 4 Bit 3..0
Initialize to 0 at connection setup. Do not change by P in normal operation. CARINS 1 Force insertion of F5 AIS Cells downstream (CIP=1). Initialize to 0 at connection setup. Do not change by P in normal operation.
'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. CEDCEN Enable Data Collection on F5 End-to-End BR cells. Related identifier CEDCID. CSDCEN Enable Data Collection on F5 Segment BR cells directly generated from F5 segment FM cells. Related identifier CSDCID. CTSDCEN Enable Data Collection on terminated / intermediate F5 Segment BR cells, related identifier CTSDCID in Dword2. Identifier for Data Collection on F5 Segment BR cells. Related enable CEDCEN. Identifier for Data Collection on F5 Segment BR cells directly generated from F5 segment FM cells. Related enable CSDCEN. Identifier for a terminating F5 Segment or End-to-End FM flow. Related enable CPMTEN in Dword0. Identifier for an originating F5 Segment or End-to-End FM flow. Related enable CPMOEN in Dword0.
Bit 30
Bit 29
Bit 28
CEDCID(6:0) CSDCID(6:0) CPMTID(6:0) CPMOID(6:0)
Data Sheet
3-115
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Dword
'RZQVWUHDP ([WHUQDO 5$0 ) (QWU\ 'ZRUGV
PEDCID(6:0) 30..15
PSDCID(6:0) 13 PPMTID(6:0) 12..9
PTSDCID(6:0) PPMOID(6:0) 4..0
7 31 6 31 30 29 28 5 31
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8765
4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31
PAR Dword parity protection. In normal operation write to 0. Should always read as 0. PPMTEN Enable a terminating F4 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier PPMTID in Dword6. PPMOEN Enable an originating F4 Segment or End-to-End FM flow. Flow type selected with PMFT in PM RAM entry. Related identifier PPMOID in Dword6. Initialize to 0 at a connection setup. Do not change by P in normal operation. PLOCF2N 1 Indication for a state transition from LOC failure state to LOC normal state. Set by AOP, reset by the P. Reported with interrupt DPSTTR if enabled with PCCMEN=1 (Dword5). Indication for a state transition from LOC defect state to LOC failure state. Set by AOP, reset by the P. Reported with interrupt DPSTTR if enabled with PCCMEN=1 (Dword5). Indication for a state transition from AIS failure state to AIS normal state. Set by AOP, reset by the P. Reported with interrupt DPSTTR if enabled with PRDIMEN=1 (Dword5).
Bit 30
Bit 29
Bit 28 Bit 27
Bit 26
PLOCD2F 1
Bit 25
PRDIF2N 1
Data Sheet
3-116
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 24
PRDID2F 1 Indication for a state transition from AIS defect state to AIS failure state. Set by AOP, reset by the P. Reported with interrupt DPSTTR if enabled with PRDIMEN=1 (Dword5). Indication for a state transition from AIS failure state to AIS normal state. Set by AOP, reset by the P. Reported with interrupt DPSTTR if enabled with PAISMEN=1 (Dword5). Indication for a state transition from AIS defect state to AIS failure state. Set by AOP, reset by the P. Reported with interrupt DPSTTR if enabled with PAISMEN=1 (Dword5).
Bit 23
PAISF2N 1
Bit 22
PAISD2F 1
Bit 21
PLBS F4 Loopback State according to I.610. Should be set before inserting a LB cell, cleared after reception of the looped cell. Reserved, set to 0. PSRCIDEN Loopback of LB Cells using LB source ID: 1 Enabled. Normally this bit is =0 as the location ID is used to detect intra-domain LB cells.
Bit 20 Bit 19
Bit 18
PLOCIDEN Loopback of LB Cells using LB location ID 1 Enabled. Normally this bit is =1 as according to the standard the location ID is used to detect intra-domain LB cells. Enable F4 processing, default. Disable F4 processing. All F4 OAM cells are discarded. Option selected e.g. at AAL interworking point. No F4 Terminating Segment Point. F4 Terminating Segment Point. Do not adjust at F4 OEP. No F4 Originating Segment Point. F4 Originating Segment Point.
Bit 17
DISF4 0 1
Bit 16
PTSP 0 1
Bit 15
POSP 0 1
Data Sheet
3-117
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 13
PIP 0 1 F4 Originating End Point (OEP). F4 intermediate Point.
Bit 12..9 Bit 8
Initialize to 0 at connection setup. Do not change by P in normal operation. PCCINS 1 Insertion of F4 CC Cells for all activated CC flows; period determined by MAXTS in register SCCONF1.
Bit 7 Bit 6 Bit 5 Bit 4..0
Initialize to 0 at connection setup. Do not change by P in normal operation. PARINS 1 Force insertion of F4 AIS Cell downstream. Initialize to 1 at connection setup. Do not change by P in normal operation. Initialize to 0 at connection setup. Do not change by P in normal operation.
'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Initialize to 0 at connection setup. Do not change by P in normal operation. PICCEN 1 Bit 13 PSCCTEN 1 Bit 12 Bit 11 Terminate a F4 Segment Continuity Check. Should only be enabled at a F4 TSP (PTSP=1). Enable Internal Continuity Check, terminating ICC in downstream direction. Set to 0 if ICC is not used.
Bit 30..15 Bit 14
Reserved, set to 0. PSCCOEN 1 Originate a F4 Segment Continuity Check. Should only be enabled at a F4 OSP (POSP=1). Originate a F4 End-to-End Continuity Check. Should only be enabled at a F4 OEP (PIP=0).
Bit 10
PECCOEN 1
Data Sheet
3-118
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 9
PRDIMEN 0 1 F4 RDI monitoring disabled. F4 RDI monitoring enabled. State transition to RDI failure state and out of RDI failure state is reported by use of the P interrupt DPSTTR. F4 AIS monitoring disabled. F4 AIS monitoring enabled. State transition to AIS failure state and out of AIS failure state is reported by use of the P interrupt DPSTTR. F4 CC monitoring disabled. F4 CC monitoring enabled. State transition to LOC failure state and out of LOC failure state is reported by use of the P interrupt DPSTTR. F4 AIS/RDI Cell insertion disabled. F4 AIS/RDI Cell insertion enabled. Independent of the reason for cell generation (forced insertion by ARINS, detected LOC or AIS state) AIS cell generation is always controlled by this flag. F4 LOC failure state indication. Initialize to 0. Do not change by P in normal operation. F4 LOC defect state indication. Initialize to 0. Do not change by P in normal operation. F4 RDI failure state indication. Initialize to 0. Do not change by P in normal operation. F4 RDI defect state indication. Initialize to 0. Do not change by P in normal operation. F4 AIS failure state indication. Initialize to 0. Do not change by P in normal operation.
Bit 8
PAISMEN 0 1
Bit 7
PCCMEN 0 1
Bit 6
PARIEN 0 1
Bit 5
PLOCFAI 1
Bit 4
PLOCDEF: 1
Bit 3
PRDIFAI: 1
Bit 2
PRDIDEF: 1
Bit 1
PAISFAI: 1
Data Sheet
3-119
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 0
PAISDEF: 1 F4 AIS defect state indication. Initialize to 0. Do not change by P in normal operation.
'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. PEDCEN Enable Data Collection on F4 End-to-End BR cells. Related identifier PEDCID. PSDCEN Enable Data Collection on F4 Segment BR cells directly generated from F4 Segment FM cells. Related identifier PSDCID. PTSDCEN Enable Data Collection on terminated / intermediate F4 Segment BR cells, related identifier PTSDCID in Dword7. Identifier for Data Collection on F4 End-to-End BR cells. Related enable PEDCEN. Identifier for Data Collection on F4 Segment BR cells directly generated from F4 Segment FM cells. Related enable PSDCEN. Identifier for a terminating F4 Segment or End-to-End FM flow. Related enable PPMTEN in Dword4. Identifier for an originating F4 Segment or End-to-End FM flow. Related enable PPMOEN in Dword4.
Bit 30
Bit 29
Bit 28
PEDCID(6:0) PSDCID(6:0) PPMTID(6:0) PPMOID(6:0)
'RZQVWUHDP ) 2$0 (QWU\ 'ZRUG Bit 31 PAR Dword parity protection. In normal operation write to 0. Should always read as 0. Identifier for Data Collection on terminated/intermediate F4 Segment BR cells, related to PTSDCEN in Dword6.
PTSDCID(6:0)
Data Sheet
3-120
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Dword
,QWHUQDO 30 0DLQ 5$0 (QWU\ 'ZRUGV
FMDIFF(15:0) BIP16(15:0) TUC(15:0)
BL(3:0) FT 8 MCSNUP(7:0)
Unused MCSN(7:0)
2 1 0
TUC0(15:0)
,QWHUQDO 30 0DLQ 5$0 (QWU\ 'ZRUG Bit 31:16 TUC(15:0) Total user cell count high and low priority cells (CLP0+1). Used at originating and terminating point. Initialized to all 0 at PM set-up. Bit 15:0 TUC0(15:0) Total user cell count high priority cells only (CLP=0). Used at originating and terminating point. Initialized to all 0 at PM set-up. ,QWHUQDO 30 0DLQ 5$0 (QWU\ 'ZRUG Bit 31:16 BIP16(15:0) Bit interleaved parity accumulated over block of user cells. Used at originating and terminating point. Initialized to all 0 at PM set-up. Bit 15:8 MCSNUP(7:0) Monitoring cell sequence number updated by the last FM cell. Used at terminating point only. Initialized to all 0 at PM set-up. Bit 7:0 MCSN(7:0) Monitoring cell sequence number running counter. Used at originating and terminating point. Initialized to all 0 at PM set-up.
Data Sheet
3-121
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
,QWHUQDO 30 0DLQ 5$0 (QWU\ 'ZRUG Bit 31:16 FMDIFF(15:0) Local TUC minus TUC from incoming FM cell at FM terminating point. FMDIFF is not used at FM originating point. Initialized to all 0 at PM setup. Bit 15:12 Block length encoding. Programmed by the microprocessor, read by the AOP. BL(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bit(11:10) FT(1:0) 00 01 10 11 Block Length 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 Flow Type F4 Segment F4 End-to-end F5 Segment F5 End-to-end
Data Sheet
3-122
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
Bit 9 Bit 8
Unused BRIDIS 0 1 Backward Reporting cell insertion enabled Backward Reporting cell insertion disabled
Bit(7:0) Dword
Unused ,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUGV
SECBMIS(31:0) SECBERR(31:0) TLOSTC0(31:0) TLOSTC(31:0) IMPB(31:0) MISC(31:0) TRANSUC0(31:0) TRANSUC(31:0) LOSTC0(31:0) LOSTC(31:0) ERRC(31:0) SECB(30:0)
13 12 11 10 9 8 7 6 5 4 3 2 31 1 0 TUCOLD(15:0) TRCCOLD(15:0)
TUC0OLD(15:0) TRCC0OLD(15:0)
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG TRCCOLD(15:0) TRCC0OLD(15:0) Offset values : used for TUCDiff calculation. Offset values : used for TUCDiff0 calculation.
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG TUCOLD(15:0) TUC0OLD(15:0) Offset values : used for TUCDiff/TRANSUC calculation. Offset values : used for TUCDiff0/TRANSUC0 calculation.
Data Sheet
3-123
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG Bit 31 SECB(30:0) FBR Set after the 1. BR cell, no Data Collection is done for 1. BR cell. Total severely errored cell blocks.
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG ERRC(31:0) Total errored cells.
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG LOSTC(31:0) Total lost cells (CLP = 0+1).
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG LOSTC0(31:0) Total lost cells (CLP = 0).
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG TRANSUC(31:0) Total transmitted user cells (CLP = 0+1).
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG TRANSUC0(31:0) Total transmitted user cells (CLP = 0).
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG MISC(31:0) Total misinserted cells.
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG IMPB(31:0) Total impaired blocks.
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG TLOSTC(31:0) Total lost cells (CLP = 0+1).
Data Sheet
3-124
04.2000
3;% (
5HJLVWHU 'HVFULSWLRQ
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG TLOSTC0(31:0) Total lost cells (CLP = 0).
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG SECBERR(31:0) Total severely errored cell blocks due to bit errors.
,QWHUQDO 30 'DWD &ROOHFWLRQ 5$0 (QWU\ 'ZRUG SECBMIS(31:0) Total severely errored cell blocks due to misinserted cells.
Data Sheet
3-125
04.2000
3;% (
2SHUDWLRQ

2SHUDWLRQ 2YHUYLHZ
This section describes the actions to be done by the microprocessor. For this purpose the following network scenario is assumed (see also )LJXUHV DQG for reference): * The OAM functions AIS/RDI/CC are always enabled for all connections (although the AOP also supports enabling on a per-connection basis). Activating the CC function by default avoids use of CC activation/deactivation cells. * For all time-out values the recommended values of the standard [] are used. * Performance monitoring is always initiated by the generating port (VHH )LJXUH ) using PM activation cells. The respective endpoint loops a cell with 'activation request confirmed' back if a PM processor is available. If all 128 PM processors are in use the 'activation request denied' cell is sent back. The deactivation cell is always confirmed. * PM data collection is always done on the port where the FM cells are generated, i.e. the BR cells are evaluated and discarded there (the AOP supports PM data collection on any point along the backward PM cell path). * Segment borders are fixed to transmission lines (although the AOP supports the perconnection definition of segment points). * At originating segment points AIS/RDI monitoring for VPCs is enabled, i.e. at the entrance of the network of an operator it is detected if a VPC is received fault-free or not. So the network operator knows at any time the availability of his VPCs. Monitoring is not activated for VCCs, as these are set-up only temporary. All these assumptions facilitate OAM management by reducing the number of parameters to be handled. *XLGHOLQHV IRU PLFURSURFHVVRU DFWLRQV
:ULWH0RGLI\5HDG$FFHVV For a normal read-modify-write access to a RAM, the following actions have to be done by the microprocessor : 1. Write the data to the write transfer registers WDR0L..WDR13H (see VHFWLRQ page 59). 2. Set the mask bits in the mask data registers MDR0L..MDR6H and WMASK (see VHFWLRQ page 60 and VHFWLRQ page 61). Note that RAM words 0..6 are bitwise masked with the MDR registers, RAM words 7..13 are masked completely by setting the corresponding bit in register WMASK). 3. Write the LCI to the address register RMWADR (see VHFWLRQ page 63). 4. Set the following bits in the read-modify-write control register RMWC (see VHFWLRQ page 62) : bits 5..4 (e.g. to '01' for external RAM), bit 2 equal to '1' for upstream or equal to '0' for downstream and bit 3 epual to '1', i.e. start of RMW. 5. The RMW is done when bit 3 of RMWC is set to '0' by the AOP. 6. Read the read transfer registers RDR0L..RDR13H (see VHFWLRQ page 60). RMW access on PM or DC RAM is the same as for the external RAM, besides that RMWADR should have a value between 0 and 127 and for PMMAIN only registers WDR0L..WDR2H, RDR0L..RDR2H, MDR0L..MDR2H are used. The entries 0..3 will be written to address LCI defined by register RMWADR, the entries 4..7 to address LCI2 defined in entry 0. Note, that read
Data Sheet 4-126 04.2000
3;% (
2SHUDWLRQ
data from a former RMW cycle is lost during write-only-access (bit 0 of register RMWC equal to '1'). During read or modify the external RAM parity-check will be done. While RMW is active, the registers RMWC and RMWADR are writeprotected. &HOO LQVHUWLRQ E\ WKH PLFURSURFHVVRU When the microprocessor should insert cells, e.g. PM or CC, follow this guideline : 1. Write the cell data into the transmit cell payload registers TXR0..26 (see VHFWLRQ page 67 and VHFWLRQ page 68). 2. If the cell is to be inserted in downstream direction set bit 0 of the transmission command register TMCR (see VHFWLRQ page 69). Otherwise set bit 1 (for upstream direction). If both bits are set to '1', the AOP reacts in the same way as if only bit 1 is set. 3. After the insertion of the microprocessor cell into the datastream, the choosen bit in register TMCR will be reset by the AOP. 5HDGLQJ RI DUULYHG FHOOV E\ WKH PLFURSURFHVVRU If a cell arrives at the AOP, the microprocessor must perform the following operations : 1. The AOP signals the availability of arrived cells by setting bit 9 of the interrupt register ISR0 (see VHFWLRQ page 83). 2. The microprocessor has to read the receive cell register RXRCEL for 27 times. 3. Bit 6 of the UDF2 octed will indicate the source of the arrived cell ('0' = downstream). 4. After the 27th read access the AOP will reset bit 9 of ISR0. The cell will be read in the same order as the transmit cell, i.e. address 80 to 9C. 6&$1 XVDJH Here is an example for the usage of the SCAN. 1. Setup the connections in the external RAM using RMW. 2. For general adjustement of the SCAN procedure, the microprocessor has to write the first LCI to be processed into register SCCONF4 (see VHFWLRQ page 80) and the last LCI to be processed into register SCCONF5 (see VHFWLRQ page 81). Write the values for SCP and SCPTOL into register SCCONF2 (see VHFWLRQ page 79 and VHFWLRQ page 48). Further some adjustments for DMA are needed when use of DMA is intended. Set bit 3 of the DMA configuration register DCONF (see VHFWLRQ page 77) to the respective value for normal or compressed mode. Additionally write the index value to the same register (bit 2..0). Write DMA data to registers DWDRL and DWDRH (see VHFWLRQ page 74 and VHFWLRQ page 74) and the RMW mask to registers DMRL and DMRH (see VHFWLRQ page 75 and VHFWLRQ page 75). At last adjustments for the OAM are needed when use of OAM is intended. Herefore setup the counter limits for state transitions in the registers SCCONF0 and SCCONF1 (see VHFWLRQ page 78 and VHFWLRQ page 79). 3. The SCAN mechanism is started by the following actions. Write respective settings to the SCAN command register SCCONF3 (see VHFWLRQ page 80). The SCAN is started by setting bit 0. This bit is reset as soon as the SCAN mechanism is started internally. 4. The SCAN is finished when the start bit is reset and bit 0 of the SCAN status register is equal to '0' (see VHFWLRQ page 81). The registers in the SCAN block are write protected during the SCAN operation.
Data Sheet
4-127
04.2000
3;% (
2SHUDWLRQ
,QLWLDOL]DWLRQ DQG 7HVW These are the actions to be performed after reset to prepare the AOP for operation. * Check reset values of all registers * Set HW configuration (RAM type, UTOPIA configuration) * Initialize internal and external RAMs For this purpose the DMA feature of the chip could be used. * Test parity detectors * Check data path (via adjacent ATM devices) &RQILJXUDWLRQ The following parameters must be known by the microprocessor for the operation of the AOP: * Number of PHYs * Edge-of-the-network or intra-network point for each PHY * Switch Port ID for intra-network Loopback * Number of supported connections * Thresholds for PM data collection values * Use of internal CC function or not. 6HWXS &OHDUGRZQ RI &RQQHFWLRQV For a connection setup the following parameters are required: * Local connection identifier LCI * VPC or VCC * If VCC the LCI2 value of the associated VP-entry (VP-pointer) * VCC endpoint indication (at AAL function) * PHY number All further programming is done using the edge-of-the-network or intra-network configuration of the PHY (for the abbreviations see 6HFWLRQ ): * In case of a VCC the upstream part of the AOP is configured as VP-TEP and the downstream part as VP-OEP. If in addition the PHY is configured as edge of a network the upstream part is configured as VC-OSP and the downstream part as VC-TSP. * In case of a VPC without a segment border both up- and downstream parts are configured as intermediate point (VP-IP). If the PHY is configured as edge of the network the upstream part is configured as VP-OSP and the downstream part as VP-TSP.
1RWH ,I D 3+< LV DW WKH HGJH RI D QHWZRUN LWV WUDQVPLVVLRQ OLQH LV FRQQHFWHG WR WKH QHWZRUN RI DQRWKHU RSHUDWRU +HQFH DOO VHJPHQW VWUHDPV DUH WHUPLQDWHG EHIRUH WKH $70 FHOOV OHDYH WKH QRGH QRQRYHUODSSLQJ PRGH
* At OEPs the CC flow generation is enabled (VPC or VCC, segment or end-to-end).
Data Sheet
4-128
04.2000
3;% (
2SHUDWLRQ
(QDEOH 'LVDEOH RI 30 This command is issued by the microprocessor either on request from the system controller or in the course of a activation/deactivation cell received for this connection. The following parameters are needed: * LCI of the connection or LCI2 of the VP-pointer * Block size 128, 256, 512 or 1024 * Mode select: 1) generate and collect data or 2) analyze and loop. 1RUPDO 2SHUDWLRQ
6FDQ 3URFHVV 7ULJJHU In fault free state the main task of the microprocessor is to trigger the scan function in 500 ms intervals. This is done by setting one single bit in a register. An internal logic checks all requested entries (from LCI min. to LCI max) of both up- and downstream external RAMs. According to the actual state of the connection (AIS state, PHY failure, CC state etc.) and the programmed timeout values the respective state transitions are performed automatically by the AOP. In addition an interrupt bit is set if a state transition to or from failure state occurred. As long as no state transition occurs nothing else has to be done by the microprocessor than to trigger the scan in 500 ms intervals. In case of an interrupt the microprocessor must determine the connection which triggered the (common) interrupt. For this purpose the compressed DMA function is enabled together with the next scan, which transfers the status dword of all connections from both up- and downstream external RAM to the microprocessor memory. The status dword contains: * VP/VC AIS/RDI/LOC defect/failure state * transition events between these states and fault-free state * error indication bits * direction bit. The compressed DMA can be programmed to clear the transition event bits after read within the same scan/DMA process (VHH )LJXUH ). The microprocessor is informed by the AOP about transitions to failure states and back to faultfree states via interrupt. According to the standards transitions to defect states are not reported. Scan and DMA completion is indicated by flags. With one 32-bit dword transferred per connection and per direction, in total up to 32 K dwords are transferred to the microprocessor memory. The dwords are stored in the designated RAM area with ascending LCI values from lower to upper LCI limit. Upstream and downstream dword of a LCI are adjacent, but their order is undetermined. The direction bit must be evaluated for each dword.
Data Sheet
4-129
04.2000
3;% (
2SHUDWLRQ
%LW 0DSSLQJ IRU &RPSUHVVHG '0$ 0RGH Dword
0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 '0' '0' 13 12 11 10 9 8 '0' '0' 5 4 3 2 1 0
7DEOH %LW 0DSSLQJ IRU &RPSUHVVHG %LW 1DPH )) 'ZRUG %LW 31 '1' : Up '0' : Down 30 Parity Error 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 PLOCF2N PLOCD2F PRDIF2N PRDID2F PAISF2N PAISD2F EDCERR OAMMIS PLOCFAI PLOCDEF PRDIFAI PRDIDEF PAISFAI PAISDEF '0' always '0' always CLOCF2N CLOCD2F F4 F4 F4 F4 F4 F4 F4 F4 F4 F4 F4 F4 F4 F4 F5 F5 4 4 4 4 4 4 2 2 5 5 5 5 5 5 2 2 27 26 25 24 23 22 13 12 5 4 3 2 1 0 19 18
'0$ 0RGH ,QGLFDWLRQ Indicates upstream or downstream external RAM. If =1 at least one dword of the LCI entry a parity error was detected. Indication for a state transition from LOC Failure state to LOC Normal state. Indication for a state transition from LOC Defect to LOC Failure state. Indication for a state transition from AIS Failure to AIS Normal state. Indication for a state transition from AIS Defect to AIS Failure state. Indication for a state transition from AIS Failure to AIS Normal state. Indication for a state transition from AIS Defect to AIS Failure state. Wrong EDC (CRC10) in an OAM cell detected. Misinserted OAM cell discarded. F4 LOC failure state indication. F4 LOC defect state indication. F4 RDI failure state indication. F4 RDI defect state indication. F4 AIS failure state indication. F4 AIS defect state indication.
Indication for a state transition from F5 LOC failure state to F5 LOC normal state. Indication for a state transition from F5 LOC defect state to F5 LOC failure state.
Data Sheet
4-130
04.2000
3;% (
2SHUDWLRQ
7DEOH %LW 0DSSLQJ IRU &RPSUHVVHG '0$ 0RGH %LW 1DPH )) 'ZRUG %LW ,QGLFDWLRQ 11 CRDIF2N F5 2 17 Indication for a state transition from F5 RDI failure state to F5 RDI normal state. 10 CRDID2F F5 2 16 Indication for a state transition from F5 RDI defect state to F5 RDI failure state. 9 CAISF2N F5 2 15 Indication for a state transition from F5 AIS failure state to F5 AIS normal state. 8 CAISD2F F5 2 14 Indication for a state transition from F5 AIS defect state to F5 AIS failure state. 7 '0' always 6 '0' always 5 CLOCFAI F5 1 5 F5 LOC failure state. 4 CLOCDEF F5 1 4 F5 LOC defect state. 3 CRDIFAI F5 1 3 F5 RDI failure state. 2 CRDIDEF F5 1 2 F5 RDI defect state. 1 CAISFAI F5 1 1 F5 AIS failure state. 0 CAISDEF F5 1 0 F5 AIS defect state.
1) 2)
Refer to the external RAM (identical for up- and downstream RAM). For detailed explanation see section 3.9.1, page 98, section 3.9.2, page 104, section 3.9.3, page 110 and section 3.9.4, page 116.
30 7KUHVKROG &KHFN Also in normal operation the local controller checks all data collection entries, compares the values with the given thresholds and if these are exceeded * Activates AIS/RDI insertion and * Informs network management Optionally records of the e.g. last 15 minutes could be collected on-board for the last 24 hours. (YHQWV Events are unpredictable for the peripheral controller. These may be interrupts from the HW or command messages received from the system controller . 7UDQVPLVVLRQ /LQH )DLOXUH Such failures are e.g. line breaks or transmitter/receiver failure. They are detected by the PHY device and usually signalled to the local controller by interrupt. If the failure is confirmed the local controller * sets the corresponding PHY error bit in a AOP register to signal the failure to the ATM layer. All ensuing actions as generation of VP-AIS or VC-AIS cells in forward direction as well as the insertion of VP-RDI or VC-RDI cells in backward direction are done automatically by the scan mechanism.
Data Sheet
4-131
04.2000
3;% (
2SHUDWLRQ
/% &HOO 7UDQVPLVVLRQ 5HFHSWLRQ The transmission of a LB cell is usually initiated by the system controller. The parameters * LCI * segment or end-to-end or intra-domain LB * the Location identifier in case of intra-domain LB must be given by the system controller. Note that in case of a segment or end-to-end LB the location and source ID are set to all ones. The microprocessor assembles the LB cell and transmits it via the AOP. A timer is started for time-out supervision. Prior to transmission the LB State bit is set for this connection. This bit causes the returning LB cell to be copied to the receive buffer. If it is not set the backward LB cell is discarded without notice. By comparing the correlation tag the peripheral controller makes sure that the cell was the one sent out before.
1RWH 7KH FRUUHODWLRQ WDJ LV QRW JHQHUDWHG E\ WKH $23 ,W LV UHFRPPHQGHG WR JHQHUDWH D UDQGRP QXPEHU E\ WKH SHULSKHUDO FRQWUROOHU
30 $FWLYDWLRQ 'HDFWLYDWLRQ &HOO 7UDQVPLVVLRQ The request to do performance monitoring over a given VPC or VCC connection or segment is initiated by the system controller and sent to the originating point microprocessor. The parameters * LCI or LCI2 (for F4 PM) * Block size (128, 256, 512, 1024) must be given. Similar to the LB procedure the microprocessor generates an appropriate activation cell for either segment or end-to-end, depending on the given configuration. After reception of the confirmation cell (6HFWLRQ ) the FM generation processor is assigned as well as a data collection processor in the opposite direction. There are two restrictions to be checked: * there are at most 128 processors for FM generation or analysis and 128 processors for data collection * not more than 2 processors can be invoked for one user cell, one for F4 and one for F5 (6HFWLRQ ). 30 $FWLYDWLRQ 'HDFWLYDWLRQ &HOO 5HFHSWLRQ An activation/ deactivation cell may be received at any time at the receive buffer of the AOP. In such a case the peripheral controller looks for a free PM processor and assigns it to the connection. The PM processor is initialized in analyzing mode. Then a confirmation cell is sent back to the originating port. The PM endpoint is now ready for reception of the first FM cell.
Data Sheet
4-132
04.2000
3;% (
2SHUDWLRQ
([DPSOHV
30 &RQILJXUDWLRQ In this example a VPC containing a VCC is terminated. A number of PM measurements are performed: * end-to-end PM at F4 (VPC) level bi-directional * segment PM termination and creation of a new segment at F5 (VCC) level uni-directional In total 4 PM processors and 2 data collection processors are involved. Their associated RAM entries are shown in )LJXUH . The two connections involved, VPCa and VCCb are represented by 2 entries in each up- and downstream RAM, a F4 and a F5 entry with the F5 entry pointing to the F4 entry. Each entry has 4 pointer + enable pairs to define: * the origination point of a PM flow * the endpoint of a PM flow * a data collection point for a end-to-end flow * a data collection point for a segment flow. For origination and termination points the selection between end-to-end and segment flows is done in the PM main RAM by setting the flow type (FT) bits. At termination points the generation of BR cells can be enabled by setting BRDIS=0. A further parameter to specify is the block length BL. In the example of )LJXUH two different block sizes are used, 1024 (coding 1001) at the F4 level and 256 (coding 0111) at the F5 level. The data collection function evaluates the contents of BR cells. It can be enabled at any point along the path of the BR cells, including the analyzing point where the BR cells are generated. In the present example the evaluation occurs at the end point of the BR cells. The scenario shown in )LJXUH can only occur at an ingress port of a switch, where VPCs are terminated. Hence the origination of a end-to-end F4 flow should not be programmed in upstream direction. Conversely in downstream direction a F4 end-to-end flow must not be enabled.
Data Sheet
4-133
04.2000
3;% (
2SHUDWLRQ
VPCa
VCCb
segment border
generate F4 end-end PM flow collect data analyze F4 end-end PM flow loop report back analyze F5 segment PM flow loop report back upstream connection RAM 16383 F4 entry of VPCa Terminate end-end or segment flow (PPMTEN + PPMTID) Originate end-end or segment flow (PPMOEN + PPMOID) Data collect end-end (PEDCEN + PEDCID) Data collect segment (PSDCID + PSDCEN) collect data generate F5 segment PM flow
F5 entry of VCCb Terminate end-end or segment flow (CPMTEN + CPMTID) Originate end-end or segment flow (CPMOEN + CPMOID) Data collect end-end (CEDCEN + CEDCID) Data collect segment (CSDCID + CSDCEN)
performance monitoring main RAM 127 FT=01 | BRDIS=0 | BL=1001 | PM data... FT=10 | BRDIS=0 | BL=0111 | PM data... FT=10 | BRDIS=1 | BL=0111 | PM data... 0 FT=01 | BRDIS=1 | BL=1001 | PM data... 0
downstream connection RAM 16383 F4 entry of VPCa Terminate end-end or segment flow (PPMTEN + PPMTID) Originate end-end or segment flow (PPMOEN + PPMOID) Data collect end-end (PEDCEN + PEDCID) Data collect segment (PSDCID + PSDCEN)
performance monitoring data collection RAM 127 PM result data (14 dwords)
PM result data (14 dwords) 0
F5 entry of VCCb Terminate end-end or segment flow (CPMTEN + CPMTID) Originate end-end or segment flow (CPMOEN + CPMOID) Data collect end-end (CEDCEN + CEDCID) Data collect segment (CSDCID + CSDCEN)
0
)LJXUH
Data Sheet
3HUIRUPDQFH 0RQLWRULQJ ([DPSOH
4-134 04.2000
3;% (
,QWHUIDFHV

,QWHUIDFHV 8723,$ ,QWHUIDFHV
The AOP has one UTOPIA receive interface and one UTOPIA transmit interface with master capability at the PHY side and one receive and transmit interface with slave capability at the ATM side (ILJXUH ). The interfaces are compliant to the UTOPIA Level 1 and 2 specification [ ], i.e.: * bus width is selectable either 8 or 16 bit * single-PHY or multi-PHY configurations * PHY number enhancement option, see specification UTOPIA Level 2 Appendix 1.
QC Tvqr VrhA8ryyAAy
6UH Tvqr
PHY (P)
ATM (A)
PHY (P)
ATM (A)
RXDATU(15:0)
TXDATU(15:0)
RXSOCU
TXSOCU
Receive Upstream Master
RXPRTYU
Transmit Upstream Slave
TXPRTYU
RXCLAVU(3:0)
TXCLAVU(3:0)
RXENBU(3:0)
TXENBU(3:0)
RXADRU(3:0)
TXADRU(3:0)
UTPHYCLK
$23
Transmit Downstream Master Receive Downstream Slave
UTATMCLK
TXDATD(15:0)
RXDATD(15:0)
TXSOCD
RXSOCD
TXPRTYD
RXPRTYD
TXCLAVD(3:0)
RXCLAVD(3:0)
TXENBD(3:0)
RXENBD(3:0)
TXADRD(3:0)
RXADRD(3:0)
9rhA8ryyAAy
)LJXUH
8723,$ ,QWHUIDFHV
Data Sheet
5-135
04.2000
3;% (
,QWHUIDFHV
Receive and transmit side of ATM and PHY side UTOPIA interface operate each from one clock which may be completely independent from the main chip clock SYSCLK. The UTOPIA clock frequency must be less than or equal to the main chip clock SYSCLK. The UTOPIA interface has an 8-bit and a 16-bit option. The 16-bit option has the 54 octet cell format shown in ILJXUH for the standardized format and in ILJXUH for the proprietary format. The 8-bit format has 53 octet without the UDF2 octet. ATM side and PHY side UTOPIA interface can be configured independently in 8-bit or 16-bit mode. bit: 0 1 2 3 4 : 26
word
15
14
13
12
11
10 9 VPI(11:0) VCI(11:0)
8
7
6
5
4
3
2 1 0 VCI(15:12) PT(2:0) CLP
UDF1 Payload Octet 1 Payload Octet 3 : Payload Octet 47
UDF2 Payload Octet 2 Payload Octet 4 : Payload Octet 48
)LJXUH
6WDQGDUGL]HG 8723,$ FHOO IRUPDW ELW DOO ILHOGV DFFRUGLQJ WR VWDQGDUGV XQXVHG RFWHWV VKDGHG 14 13 10 9 8 LCI(11:0) VCI(11:0) HK(2:0) PN(2:0) Payload Octet 1 Payload Octet 3 : Payload Octet 47 12 11 7 6 5 4 3 2 1 0 VCI(15:12) PT(2:0) CLP
bit: 0 1 2 3 4 : 26
word
15
/&,
UDF2 Payload Octet 2 Payload Octet 4 : Payload Octet 48
)LJXUH with
3URSULHWDU\ 8723,$ FHOO IRUPDW ELW
PN(2:0) = port number for PXB 4220 IWE8 (don't care for AOP) HK(2:0) = housekeeping bits (only for Internal Continuity Check ICC) LCI(13:0) = Logical Connection Identifier all other fields according to standards, unused octets shaded. 8723,$ 0XOWL3+< VXSSRUW To support multi-PHY configurations with and without use of the UTOPIA PHY address the Infineon Technologies ATM switching chip set supports the Direct Status Polling option of the UTOPIA Level 2 standard []. It allows the simultaneous polling of up to 4 groups of PHYs by using 4 CLAVx/ENx signal pairs (x=0..3). During the transfer of a cell the master UTOPIA interface polls 12 PHY addresses. The 27 clock cycles time for the transfer of a cell in 16-bit UTOPIA format allows to poll 12 PHY addresses and to select one of them for the next cell transfer. Receive and transmit UTOPIA interfaces always poll separately. To allow the support of more than 12 PHYs 4 pairs of CLAVx/ENx lines are provided in all Infineon Technologies ATM switching chips with UTOPIA interfaces.
Data Sheet 5-136 04.2000
3;% (
,QWHUIDFHV
However, although 48 PHYs could be polled by this configuration only up to 24 PHY are supported.
1RWHWKH QXPEHU RI OLQH LQWHUIDFHV 3+25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s 25.6 Mbit/s
slave
PHY1 Port 6..11 device 1 Adr 0..5
slave
PHY0 Port 0..5 device 0 Adr 0..5
RxEnb0 RxCLAV0 RxEnb1 RxCLAV1 RxEnb2
PHY2 Port 12..17 device 2 Adr 0..5
RxCLAV2
UTOPIA Interface of ATM layer device e.g. PXB 4350 E ALP PXB 4340 E AOP PXB 4330 E ABM
RxEnb3
PHY3 Port 18..23 device 3 Adr 0..5
RxCLAV3 RxAdr(3:0) RxBUS(9:0) UTCLK RxBUS(9:0) = RxSOC : RxPrty : RxDat(7:0) UTCLK
)LJXUH
8SVWUHDP UHFHLYH 8723,$ H[DPSOH IRU [ 3+There are four different operating modes for the UTOPIA interface. Three of them are multi-PHY modes which use the address bus. One additional mode is provided, for connecting Level 1 PHY chips without address inputs. All modes are summarized in 7DEOH .
Data Sheet
5-137
04.2000
3;% (
,QWHUIDFHV
7DEOH
8723,$ SROOLQJ PRGHV 7KH QXPEHUV LQGLFDWH WKH RIIVHW ZKLFK LV DGGHG WR WKH 3+< QXPEHU 0RGH [ 0RGH [ 0 8 16 do not connect 0RGH [ 0 6 12 18 /HYHO 0RGH 0 0 0 0 0 12 do not connect do not connect
EN0 / CLAV0 EN1 / CLAV1 EN2 / CLAV2 EN3 / CLAV3
The poll cycle is identical in all modes, i.e. the address lines output all addresses from 0 to 11 during one cell cycle. In one polling cycle all PHYs are polled. If the address is greater than the number of PHYs at the device, the associated CLAVx is set to 0. The real PHY number depends on the selected mode. The polling sequence of the next polling cycle depends on the current transmitting PHY, e.g. if PHY5 is the current transmitter the next polling sequence is as follows: PHY6,PHY7,...,PHY11,PHY1,PHY2,...,PHY5. In this case, PHY6 has the highest priority and PHY5 the lowest. PHY5 is polled at byte 48 of the payload only when no other PHY is selected. The selection of the next device also depends on the current device. If the current transmitter is from device 2, the next polling cycle starts with the device 3 (highest priority), then device 4, device 1 and device 2 (lowest priority). * In Level 1 mode the PHY numbers are identical to the CLAV/EN group: 0, 1, 2, 3. * It is the users responsibility to program the PHY numbers in a way that ambiguous PHY numbers inside the ATM layer device are avoided. * The mode selection can be done independently for the PHY side and the ATM side UTOPIA interface (see VHFWLRQ page 87 and VHFWLRQ page 88). * If less than or equal to 12 PHYs are to be polled, mode 2 x 12 should only be used with the CLAV0/EN0 pair connected. This minimizes the number of interconnection lines between the chips. Examples: 1. One PHY device, e.g. a 622 Mbit/s PHY: 16-bit bus width, address lines unconnected, RxCLAV0/RxEN0 and TxCLAV0/TxEN0 signal pairs connected, all other CLAVx/ENx pairs unconnected (Level 1 Mode). 2. 4 PHY devices 155.52 Mbit/s PHYs: 16-bit bus width, address lines unconnected, all 4 CLAVx/ENx pairs connected, one to each PHY device. 3. 4 PHY devices of 6-fold 25.6 Mbit/s PHYs: 16-bit bus width, address and all 4 CLAVx/ENx pairs connected, one to each PHY device (Mode 4x6, see ILJXUH ). The 4 CLAVx/ENx lines are connected one-to-one to 4 PHY devices, each containing 6 PHYs of 25.6 Mbit/s. In this example the maximum number of 24 PHYs is connected. The AOP gets 4 CLAVx signals with each polled address. All PHY devices have the addresses 0..5 assigned to their PHYs. Addresses greater than 5 always return CLAVx=0 when polled. In order to distinguish the PHYs the UTOPIA interface of the AOP adds offset numbers, e.g. 6, 12 and 18 in mode 4x6, to the PHY numbers from PHY device 1, 2 and 3, respectively. Then within the ATM layer device the PHY numbers range from 0..23 without ambiguity. 4. 4 PXB 4220 IWE8s: 8-bit bus width, address bus unconnected, all 4 CLAVx/ENx pairs connected, one to each IWE8 (this mode requires the PXB 4350 E ALP).
Data Sheet
5-138
04.2000
3;% (
,QWHUIDFHV
5$0 ,QWHUIDFHV
The AOP uses external, synchronous, static RAM (SSRAM) for the storage of connection related OAM data. Two identical SSRAM interfaces are provided, one for each direction. The SSRAM chips are operated with the system clock of up to 52 MHz. All memory entries are protected with a parity bit at the MSB location. The size of the SSRAM is depending on the number of supported connections: 8 dwords of 32bit are required per connection. Using SSRAM devices of 1 Mbit or 2 Mbit size, i.e. 32 K x 32 bit and 64 K x 32 bit, respectively, the possible memory configurations are: * 2 x 2 Mbit or 4 x 1 Mbit SSRAM for 16384 connections * 1 x 2 Mbit or 2 x 1 Mbit SSRAM for 8192 connections * 1 x 1 Mbit SSRAM for 4096 connections These are the values for one direction. Both up- and downstream external memory should always be configured symmetrical. The selection 1 Mbit or 2 Mbit SSRAM chips is done via register bits. )LJXUH shows an example of maximum RAM size with two 2 Mbit devices, ILJXUH shows an example of maximum RAM size with four 1 Mbit devices.
x = U for upstream, D for downstream RAM
2x2M configuration
RDATx(31:0) RCE3x RADRx(14:0) RADVx ROEx RGWx
IO(31:0) A(15) A(14:0) A DV OE GW CLK
0
1
RCE1x
CE of RAM No. 1 CE of RAM No. 0
3;% ( $23
RCE0x RSCx ADSC
. [ ELW 665$0
+3.3 V
+3.3 V +3.3 V
10 k 10 k 10 k 1 k
ADSP BWE CE2 CE2 BW1 BW2 BW3 BW4 MODE
GND
226 SYSCLK GND
ZZ
)LJXUH
Data Sheet
8SVWUHDP RU GRZQVWUHDP 5$0 LQWHUIDFH XVLQJ 0ELWV 5$0V
5-139 04.2000
3;% (
,QWHUIDFHV
x = U for upstream, D for downstream RAM
RDATx(31:0)
IO(31:0)
0
1
2
3
RADRx(14:0) RADVx ROEx RGWx
A(14:0) ADV O E GW CLK
RCE3x RCE2x RCE1x
CE of RAM No. 3 CE of RAM No. 2 CE of RAM No. 1 CE of RAM No. 0
3;% ( $23
RCE0x RSCx AD SC
. [ ELW 665$0
+3.3 V
+3.3 V +3.3 V
10 k 10 k 10 k 1 k
AD SP BW E C E2 CE2 BW1 BW2 BW3 BW4 MOD E
GND
226 SYSCLK GND
ZZ
)LJXUH
8SVWUHDP RU GRZQVWUHDP 5$0 ,QWHUIDFH XVLQJ 0ELW 5$0V
Note that RCEx2 is unused and RCEx3 is used as additional address pin adr(15) when using 2 Mbit RAMs.The AOP uses 4-bursts to access the external RAMs. )LJXUH shows an example for the read access. During each cell cycle two 4-burst read and two 4-burst write accesses are made at both up- and downstream RAM. If no cell is to be processed at one of the interfaces a scan/DMA access or microprocessor access is executed.
Data Sheet
5-140
04.2000
3;% (
,QWHUIDFHV
Burst Read 1 SYSCLK 2 3 4 5 6 7 8 9 10 11
ADSC
ADV
A(17:0)
A1
A2
GW
CE
OE
RDATx Input
D1 (A1)
D2 (A1)
D3 (A1)
D4 (A1)
D5 (A2)
D6 (A2)
D7 (A2)
D8 (A2)
D1..D8 A1 A2
Dwords 1..8 from external RAM Address from RMW Address Register Address LCI2 from external RAM entry
)LJXUH
([DPSOH RI ([HFXWLRQ 7LPLQJ IRU 5HDG &\FOHV %XUVW 0RGH
0LFURSURFHVVRU ,QWHUIDFH
The AOP has a 16-bit microprocessor interface for control and operation. It is identical for all devices of the Infineon Technologies ATM switching chip set . A possible microprocessor could be the 386EX embedded controller as shown in ILJXUH .
Data Sheet
5-141
04.2000
3;% (
,QWHUIDFHV
MPDAT(15:0)
MPADR(7:0) MPWR
3;% ( $23
MPRD MPCS MPINT MPRDY * MPDREQ MPDACK
PLFURSURFHVVRU
(;
1RWH 6WDWHPDFKLQHV IRU JOXH ORJLF DYDLODEOH XSRQ UHTXHVW
)LJXUH
0LFURSURFHVVRU ,QWHUIDFH
The interface is operating completely asynchronous to the system clock SysClk. -7$*%RXQGDU\ 6FDQ ,QWHUIDFH
This interface contains the boundary scan of all signal pins according to the standard []. It consists of the pins shown in ILJXUH .
TCK TMS TDI TRST
3;% ( $23
TDO
)LJXUH
-7$* ,QWHUIDFH
7HVW ,QWHUIDFH
There are several additional test pins provided for board test. Please let them unconnected or connected to ground as described in section 5.6, part "Additional Testpins".
Data Sheet 5-142 04.2000
3;% (
3LQ 'HVFULSWLRQ
3LQ 'HILQLWLRQV DQG )XQFWLRQV
The following explanations applies for all Pins of a field in the table respectively: * Pins with a 1) attached are connected with an internal pull up resistor. * Pins with a 2) attached are connected with an internal pull down resistor. * Pins with a 3) attached are 5V compatible. Pin Definitions and Functions 3LQ 1R 6\PERO ,QSXW , 2XWSXW 2 &ORFN DQG UHVHW SLQV AC26 B12 A13 AE14 RESET SYSCLK UTPHYCLK UTATMCLK I I I I Chip reset Main chip clock UTOPIA clock at PHY side (master). UTOPIA clock at ATM side (slave).
)XQFWLRQ
8WRSLD,QWHUIDFH UHFHLYH XSVWUHDP PDVWHU SLQV B20, A20, C20, B19, D18, A19, C19, B18, A18, B17, C18, A17, D17, B16, C17, A16 2) C23, A23, B22, D22 A21 2) A25, B24, A24, B23 A22, B21, D20, C21 2) C22 2) RXDATU (15:0) I Receive data bus from PHY side.
RXADRU (3:0) RXPRTYU RXENBU (3:0) RXCLAVU (3:0) RXSOCU
O I O I I
Address outputs to PHY side. Odd parity of RXDATU(15:0) from PHY side. Enable signal to PHY side. Cell available signal from PHY side. Start of cell signal from PHY side.
Data Sheet
5-143
04.2000
3;% (
3LQ 'HVFULSWLRQ
Pin Definitions and Functions 3LQ 1R 6\PERO ,QSXW , 2XWSXW 2
)XQFWLRQ
8WRSLD,QWHUIDFH WUDQVPLW GRZQVWUHDP PDVWHU SLQV D12, B10, C11, A10, D10, B9, C10, A9, B8, A8, C9, B7, D8, A7, C8, B6 D13, A12, B11, C12 A11 A15, C16, B14, D15 D7, A6, C7, B5 2) B15 TXDATD (15:0) O Transmit data bus to PHY side.
TXADRD (3:0) TXPRTYD TXENBD (3:0) TXCLAVD (3:0) TXSOCD
O O O I O
Address to PHY side. Odd parity to PHY side. Enable signal to PHY side. Cell available signal from PHY side. Start of cell signal to PHY side.
8WRSLD,QWHUIDFH UHFHLYH GRZQVWUHDP VODYH SLQV AF9, AE9, AD8, AF8, AC9, AE8, AD7, AF7, AE7, AF6, AD6, AC7, AE6, AF5, AD5, AC5 2) AD11, AF12, AE12, AF11 2) AE5 2) RXDATD (15:0) I Receive data bus from ATM side.
RXADRD (3:0) RXPRTYD
I I I O I
Address from ATM side. Odd parity of RXDATD(15:0) from ATM side. Enable signals from ATM side. Cell available signal to ATM side. Start of cell signal from ATM side.
AD12, AF13, RXENBD AC12, AE13 1) (3:0) AE11, AC10, RXCLAVD AF10, AD9 (3:0) AD10 2) RXSOCD
Data Sheet
5-144
04.2000
3;% (
3LQ 'HVFULSWLRQ
Pin Definitions and Functions 3LQ 1R 6\PERO ,QSXW , 2XWSXW 2
)XQFWLRQ
8WRSLD,QWHUIDFH WUDQVPLW XSVWUHDP VODYH SLQV AD18, AF19, AE19, AF18, AD17, AE18, AC17, AF17, AD16, AE17, AC15, AF16, AD15, AE16, AF15, AD14 AE23, AD21, AF22, AE21 2) AE15 TXDATU (15:0) O Transmit data bus to ATM side.
TXADRU (3:0) TXPRTYU
I O I O O
Address from ATM side. Odd parity of RXDATU(15:0) to ATM side. Enable signal from ATM side. Cell available signal to ATM side. Start of cell signal to ATM side.
AD23, AE24, TXENBU AD22, AF23 1) (3:0) AD19, AF20, TXCLAVU AC19, AE20 (3:0) AD13 TXSOCU
0LFURSURFHVVRU ,QWHUIDFH SLQV E2, E4, E3, E1, F2, G4, F3, F1, G2, G1, G3, H2, J4, H1, H3, J2 C4, B3, C5, A4, D5, B4, C6, A5 B1 C2 A3 D1 3) D3 D2 C1 MPDAT (15:0) I/O Microprocessor data bus
MPADR (7:0) MPWR MPRD MPCS MPINT MPDREQ MPRDY MPDACK
I
Address from microprocessor
I I I O O O I
Write enable from microprocessor. Read enable from microprocessor. Chip select from microprocessor. Interrupt request to microprocessor. DMA request to microprocessor. Ready output to microprocessor for read and write accesses. P DMA acknowledgment
Data Sheet
5-145
04.2000
3;% (
3LQ 'HVFULSWLRQ
Pin Definitions and Functions 3LQ 1R 6\PERO ,QSXW , 2XWSXW 2
)XQFWLRQ
&RQQHFWLRQ 'DWD 665$0 8SVWUHDP SLQV L25, M24, L26, M23, K25, L24, K26, K23, J25, K24, J26, H25, H26, J24, G25, H23, G26, H24, F25, G23, F26, G24, E25, E26, F24, D25, E23, D26, E24, C25, D24, C26 2) R25, T26, U24, T25, M26, N24, M25, T24, R26, V25, V26, U25, V24, U26, U23 P24 N23 N25 P25 R23 P26 R24 N26 RDATU (31:0) I/O Databus of Upstream Connection RAM
RADRU (14:0)
O
Addressbus of Upstream Connection RAM
RADVU ROEU RGWU RCE0U RCE1U RCE2U RCE3U RSCU
O O O O O O O O
Address Advance Input Output Enable Global Write Chip Enable RAM 0 Chip Enable RAM 1 Chip Enable RAM 2, not used in 2x2M mode Chip Enable RAM 3 or Adr(15) in 2x2M mode Status Controller RAM
Data Sheet
5-146
04.2000
3;% (
3LQ 'HVFULSWLRQ
Pin Definitions and Functions 3LQ 1R 6\PERO ,QSXW , 2XWSXW 2
)XQFWLRQ
&RQQHFWLRQ 'DWD 665$0 'RZQVWUHDP SLQV T3, U1, U4, V2, U3, V1, W2, W1, V3, Y2, W4, Y1, W3, AA2, Y4, AA1, Y3, AB2, AB1, AC2, AB4, AC1, AB3, AD2, AC3, AD1, AF2, AE3, AF3, AE4, AD4, AF4 2) N2, L3, M1, L1, K3, U2, R4, N1, M4, J1, K2, J3, K1, K4, L2 T1 T2 R1 P1 N3 R2 P3 R3 RDATD (31:0) I/O Databus of Downstream Connection RAM
RADRD (14:0)
O
Address bus of Downstream Connection RAM
RADVD ROED RGWD RCE0D RCE1D RCE2D RCE3D RSCD
O O O O O O O O
Address Advance Input Output Enable Global Write Chip Enable RAM 0 Chip Enable RAM 1 Chip Enable RAM 2, not used in 2x2M mode Chip Enable RAM 3 or Adr(15) in 2x2M mode Status Controller RAM
Data Sheet
5-147
04.2000
3;% (
3LQ 'HVFULSWLRQ
Pin Definitions and Functions 3LQ 1R 6\PERO ,QSXW , 2XWSXW 2 'HWHFWRU ,QWHUIDFH SLQV W25 FPCT2D O
)XQFWLRQ
Cell Filter 2 detector output downstream. In case of match a high pulse of 30 SYSCLK cycles is output. Minimum low period between 2 pulses is 2 SYSCLK cycles. Cell Filter 1 detector output downstream. In case of match a high pulse of 30 SYSCLK cycles is output. Minimum low period between 2 pulses is 2 SYSCLK cycles. Cell Filter 2 detector output upstream. In case of match a high pulse of 30 SYSCLK cycles is output. Minimum low period between 2 pulses is 2 SYSCLK cycles. Cell Filter 1 detector output upstream. In case of match a high pulse of 30 SYSCLK cycles is output. Minimum low period between 2 pulses is 2 SYSCLK cycles.
V23
FPCT1D
O
W26
FPCT2U
O
W24
FPCT1U
O
7HVW-7$* %RXQGDU\ 6FDQ SLQV AF24 1) TDI I Test data input; this pin has an internal pull-up resistor and need not to be connected for normal operation. Test clock; this pin has an internal pull-up resistor and need not to be connected for normal operation. Test mode select this pin has an internal pull-up resistor and need not to be connected for normal operation. TAP Controller Reset this pin has an internal pull-down resistor and need not to be connected for normal operation. If connected it must be driven to VSS for normal operation. Test data output; need not to be connected for normal operation.
AC14 1)
TCK
I
AD25 1)
TMS
I
AD26 1)
TRST
I
AE26
TDO
O
Data Sheet
5-148
04.2000
3;% (
3LQ 'HVFULSWLRQ
Pin Definitions and Functions 3LQ 1R 6\PERO ,QSXW , 2XWSXW 2 $GGLWLRQDO 7HVWSLQV SLQV AC25 1) AC24 1) Y23 2) AB25 AA24 AB23, AB24, AB26, AA25 AA26, Y25, Y26, Y24 OUTTRI UTTRI STEST AOPIIDD NDTRO TSTBUSI TSTBUSO I I I I O I O
)XQFWLRQ
For test only, do not connect For test only, do not connect For test only, do not connect Has to be connected to ground. For test only, do not connect Testbus in For test only, don't connect. Testbus out For test only, don't connect.
6XSSO\ SLQV D6, D11, D16, D21, F4, F23, L4, L23, T4, VDD, Chip 3.3 V supply T23, AA4, AA23, AC6, AC11, AC16, AC21 A1, A2, A26, B2, B25, B26, C3, C24, D4, VSS, Chip ground D9, D14, D19, D23, H4, J23, N4, P23, V4, W23, AC4, AC8, AC13, AC18, AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF25, AF26 8QFRQQHFWHG 3LQV SLQV A14, B13, C13, C14, C15, M2, M3, P2, P4, not connected pins AA3, AC20, AC22, AD20, AE10, AE22, AF14, AF21
Data Sheet
5-149
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
7DEOH
(OHFWULFDO &KDUDFWHULVWLFV $EVROXWH 0D[LPXP 5DWLQJV $EVROXWH 0D[LPXP 5DWLQJV 6\PERO 7A 7stg 9DD 9S VESD,HBM /LPLW 9DOXHV -40 to 85 -40 to 125 -0.3 to 3.6 -0.4 to 9DD + 0.4 2500 8QLW C C V V V
3DUDPHWHU Ambient temperature under biasPXB Storage temperature IC supply voltage with respect to ground Voltage on any pin with respect to ground ESD robustness1) HBM: 1.5 k, 100 pF
1)
According to MIL-Std 883D, method 3015.7 and ESD Association Standard EOS/ESD-5.1-1993. The RF Pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 V (versus 9S or GND). The high frequency performance prohibits the use of adequate protective structures. 6WUHVVHV DERYH WKRVH OLVWHG KHUH PD\ FDXVH SHUPDQHQW GDPDJH WR WKH GHYLFH ([SRVXUH WR DEVROXWH PD[LPXP UDWLQJ FRQGLWLRQV IRU H[WHQGHG SHULRGV PD\ DIIHFW GHYLFH UHOLDELOLW\
1RWH
2SHUDWLQJ 5DQJH
7DEOH 2SHUDWLQJ 5DQJH 3DUDPHWHU 6\PERO Ambient temperature under bias Junction temperature Supply voltage Ground Power dissipation
1RWH 1RWH
7A 7J 9DD 9SS 3
/LPLW 9DOXHV PLQ PD[ -40 85 125 3.45 0 1.9
8QLW C C V V W
7HVW &RQGLWLRQ
3.15 0
,Q WKH RSHUDWLQJ UDQJH WKH IXQFWLRQV JLYHQ LQ WKH FLUFXLW GHVFULSWLRQ DUH IXOILOOHG 7KH QRPLQDO VXSSO\ YROWDJH 9'' VKRXOG QRW H[FHHG 9 WR NHHS WKH GHYLFH ZLWKLQ WKH VSHFLILHG FXUUHQW DQG SRZHU GLVVLSDWLRQ UDQJHV
Data Sheet
6-150
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
'& &KDUDFWHULVWLFV '& &KDUDFWHULVWLFV 6\PERO 1RWHV
7DEOH 3DUDPHWHU
/LPLW 9DOXHV 8QLW PLQ W\S PD[ *HQHUDO ,QWHUIDFH /HYHOV (does not apply to Boundary Scan Interface): Input low voltage 9IL -0.4 0.8 V Input high voltage 9IH 2.0 9DD + V 0.3 2.1 for pin TRST Output low voltage 9OL 0.2 0.4 V
LVTTL (3.3V)
,OL = 4 mA (,OL = 6 mA for TXCLAV/ RXCLAV signals) ,OH = - 4 mA (,OH = -6 mA for TXCLAV/ RXCLAV signals) 9DD = 3.45 V, SYSCLK = 52MHz; UTPHYCLK = 52MHz; UTATMCLK = 52MHz; 9DD = 3.45 V, SYSCLK = 52MHz; UTPHYCLK = 52MHz; UTATMCLK = 52MHz; 9DD = 3.45 V, SYSCLK = 52MHz; UTPHYCLK = 52MHz; UTATMCLK = 52MHz;
Output high voltage(s) 9OH 2.4 9DD
V
Average power supply current
,CC (AV)
395
550
mA
Average power up supply current (N SYSCLK cycles after reset)
,CCPU (AV)
550
mA
Average power dissipation
3 (AV)
1.3
1.9
W
Data Sheet
6-151
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
3DUDPHWHU Input current
6\PERO ,IIN
/LPLW 9DOXHV PLQ W\S PD[ -1 1 50 150
8QLW mA mA
1RWHV 9IN = 9DD or 9SS 9IN = 9DD for Inputs with internal PullDown resistor 9IN = 9SS for Inputs with internal Pull-Up resistor 9DD = 3.3 V, GND = 0 V, 9IN = 9DD or9SS, 9OUT in TriState
-50
-200
mA
Output leakage current
,OZ
-1
1
mA
Data Sheet
6-152
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
$& &KDUDFWHULVWLFV
7A = -40 to 85 xC, 9CC = 3.15 V .. 3.45 V, 9SS = 0 V All inputs are driven to 9IH = 2.4 V for a logical 1 and to 9IL = 0.4 V for a logical 0 All outputs are measured at 9H = 2.0 V for a logical 1 and at 9L = 0.8 V for a logical 0 The AC testing input/output waveforms are shown below.
VH
Test Points
VH
Device under Test
VL
VL
CLOAD = 50 pF max
ac_int.ds4
)LJXUH
,QSXW2XWSXW :DYHIRUP IRU $& 0HDVXUHPHQWV
7DEOH &ORFN )UHTXHQFLHV 3DUDPHWHU Core clock UTOPIA clock at PHY-side UTOPIA clock at ATM-side P clock
1)
6\PERO PLQ SYSCLK UTPHYCLK UTATMCLK 25 ISYSCLK/2 ISYSCLK/2 25
/LPLW 9DOXHV PD[ 52 ISYSCLK ISYSCLK ISYSCLK
8QLW MHz MHz MHz MHz
1)
Supplied only to external microprocessor;
Data Sheet
6-153
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
0LFURSURFHVVRU ,QWHUIDFH 7LPLQJ
0LFURSURFHVVRU :ULWH &\FOH 7LPLQJ
MPADR
1 9
MPCS
2 8
MPWR
10 3 5 6 11
MPRDY
4 7
MPDAT
)LJXUH
0LFURSURFHVVRU ,QWHUIDFH :ULWH &\FOH 7LPLQJ
7DEOH 0LFURSURFHVVRU ,QWHUIDFH :ULWH &\FOH 7LPLQJ 1R 3DUDPHWHU /LPLW 9DOXHV 0LQ 7\S 0D[ 1 MPADR setup time before MPCS low 0 2 3 4 5 6 7 8 9 10 11 MPCS setup time before MPWR low MPRDY low delay after MPWR low MPDAT setup time before MPWR high Pulse width MPRDY low MPRDY high to MPWR high MPDAT hold time after MPWR high MPCS hold time after MPWR high MPADR hold time after MPWR high MPCS low to MPRDY low impedance MPCS high to MPRDY high impedance 0 1 5 3 SYSCLK cycles 5 5 5 5 1 10 15 4 SYSCLK cycles 15
8QLW ns ns ns ns
ns ns ns ns ns ns
Data Sheet
6-154
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
0LFURSURFHVVRU 5HDG &\FOH 7LPLQJ
MPADR
21 29
MPCS
22 28
MPRD
32 23 24 26 33
MPRDY
30 25 27
MPDAT
31
)LJXUH
0LFURSURFHVVRU ,QWHUIDFH 5HDG &\FOH 7LPLQJ
7DEOH 0LFURSURFHVVRU ,QWHUIDFH 5HDG &\FOH 7LPLQJ 1R 3DUDPHWHU /LPLW 9DOXHV 0LQ 7\S 0D[ 21 MPADR setup time before MPCS low 0 22 23 24 24 24 25 26 27 28 29 30 31 MPCS setup time before MPRD low MPRDY low delay after MPRD low Pulse width MPRDY low Pulse width MPRDY low (MPADR = 9DH) Pulse width MPRDY low (MPADR = B6H) MPDAT valid before MPRDY high MPRDY high to MPRD high MPDAT hold time after MPRD high MPCS hold time after MPRD high MPADR hold time after MPRD high MPRD low to MPDAT low impedance MPRD high to MPDAT high impedance 0 1 4 SYSCLK cycles 6 SYSCLK cycles 7 SYSCLK cycles 5 5 2 5 5 1 2 15 15 15 5 SYSCLK cycles 7 SYSCLK cycles 8 SYSCLK cycles
8QLW ns ns ns
ns ns ns ns ns ns ns
Data Sheet
6-155
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
7DEOH 0LFURSURFHVVRU ,QWHUIDFH 5HDG &\FOH 7LPLQJ 1R 3DUDPHWHU /LPLW 9DOXHV 0LQ 7\S 0D[ 32 MPCS low to MPRDY low impedance 1 10 33 MPCS high to MPRDY high impedance 15
8QLW ns ns
'0$ 5HTXHVW 7LPLQJ For DMA operation the MPDREQ signal is necessary. It indicates that at least one more word is available within the AOP DMA buffer. When the microprocessor reads the last word in the buffer (DMAR register) it must be ensured that the MPDREQ signal is updated early enough to prohibit another read to the DMAR register. With asynchronous sampling of the microprocessor MPDREQ input, MPDREQ has to be updated at least 1 CLKOUT cycle before the MPRDY gets active (386EX User manual, "12.2.5 Ending DMA Transfers", page 12-11). In AOP MPDREQ update is done 5 SYSCLK cycles (= 96ns at 51.84 Mhz) before MPRDY. With 25 Mhz microprocessor clock (CLK2) the CLKOUT period (twice the CLK2 period) of 80 ns is satisfied. Less than 25 Mhz microprocessor clock frequency may cause problems. If MPDREQ gets inactive the AOP waits for MPDACK = 'high', afterwards additional 20 SYSCLK cycles (about 400ns) are spent until MPDREQ will become active again. This minimum gap was introduced to ensure co-operation with the 80386EX internal DMA controller. For distinction of 2 successive read cycles the read signal must be '1' for at least 1 SYSCLK cycle, the chip select signal may remain active. This 'command inactive time' is necessary for all adjacent microprocessor read and write accesses.
Data Sheet
6-156
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
ASIC not ready => one more T2 80ns PH2 386EX:CLK2 T1 386EX:CLKOUT T2 T2 PH1 PH2 PH1 PH2 PH1
ASIC ready
PH2
386EX:RD
386EX:DRE

386EX:DACK
+30ns RD output delay +40ns synchronisation in ASIC +20ns DRE output delay
Note: Time values given in this figure are example values and not tested in production.
-80ns async DRE sampling before READY 200ns
)LJXUH
0LFURSURFHVVRU '0$ ,QWHUIDFH
7DEOH 0LFURSURFHVVRU '0$ LQWHUIDFH 1R 3DUDPHWHU 0LQ 40 41 42 Rising edge of MPDREQ after MPRD low 1 MPDREQ driven high before high impedance Interval between MPDREQ active phases (in case of successive accesses) Interval between MPDACK inactive and subsequent MPDREQ active 1 20
/LPLW 9DOXHV 7\S 0D[ 3 1
8QLW SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles
43 44
20 5
MPDREQ inactive before MPRDY active 5 (in case the DMA FIFO gets empty during the current read access)
SYSCLK cycles
Data Sheet
6-157
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
8723,$ ,QWHUIDFH
The AC characteristics of the UTOPIA Interface fulfill the standard of [1] and [2]. Setup and hold times of the 50 MHz UTOPIA Specification are valid. According to the UTOPIA Specification, the AC characteristics are based on the timing specification for the receiver side of a signal. The setup and the hold times are defined with regards to a positive clock edge, see )LJXUH . Taking into account the actual clock frequency (up to the maximum frequency), the corresponding (min. and max.) transmit side "clock to output" propagation delay specifications can be derived. The timing references (tT5 to tT12) are according to the data found in 7DEOH to 7DEOH .
&ORFN
6LJQDO
84, 86
85, 87
input setup to clock input hold from clock
)LJXUH
6HWXS DQG +ROG 7LPH 'HILQLWLRQ 6LQJOH DQG 0XOWL3+<
Data Sheet
6-158
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
)LJXUH shows the tristate timing for the multi-PHY application (multiple PHY devices, multiple output signals are multiplexed together).
&ORFN
88 89
6LJQDO
90 91
signal going low impedance from clock
signal going low impedance to clock
signal going high signal going high impedance from clock impedance to clock
)LJXUH
7ULVWDWH 7LPLQJ 0XOWL3+< 0XOWLSOH 'HYLFHV 2QO\
Data Sheet
6-159
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
,QWHUIDFH DQG VLJQDO QDPLQJ FRQYHQWLRQV
QC Tvqr VrhA8ryyAAy
6UH Tvqr
PHY (P)
ATM (A)
PHY (P)
ATM (A)
RXDATU(15:0)
TXDATU(15:0)
RXSOCU
TXSOCU
Receive Upstream Master
RXPRTYU
Transmit Upstream Slave
TXPRTYU
RXCLAVU(3:0)
TXCLAVU(3:0)
RXENBU(3:0)
TXENBU(3:0)
RXADRU(3:0)
TXADRU(3:0)
UTPHYCLK
$23
Transmit Downstream Master Receive Downstream Slave
UTATMCLK
TXDATD(15:0)
RXDATD(15:0)
TXSOCD
RXSOCD
TXPRTYD
RXPRTYD
TXCLAVD(3:0)
RXCLAVD(3:0)
TXENBD(3:0)
RXENBD(3:0)
TXADRD(3:0)
RXADRD(3:0)
9rhA8ryyAAy
)LJXUH
,QWHUIDFH 1DPLQJ &RQYHQWLRQV
In the following tables, AP (column DIR, Direction) defines a signal from the ATM Layer (transmitter, driver) to the PHY Layer (receiver), AP defines a signal from the PHY Layer (transmitter, driver) to the ATM Layer (receiver).
Data Sheet
6-160
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
All timings also apply to UTOPIA Level 1 8-bit data bus operation. The direction notification in the following tables apply to the UTOPIA master interface (AOP to PHY) 7DEOH 1R 80 81 82 83 84 TXDATU [15:0], TXSOCU TXPRTYU, TXCLAVU[0] TXENBU[0] A>P A

8QLW MHz % % ns ns
85 86 87
Input hold from ATM Clk Input setup to ATM Clk Input hold from ATM Clk
1 4 1
-
ns ns ns
7DEOH 1R 80 81 82 83 84 85 86 87 86 87
5HFHLYH 7LPLQJ 8SVWUHDP %LW 'DWD %XV 0+] DW &HOO ,QWHUIDFH 6LQJOH 3+< 6LJQDO 1DPH ',5 'HVFULSWLRQ /LPLW 9DOXHV 0LQ 0D[ PHY Clk frequency (nominal) PHY Clk duty cycle PHY Clk peak-to-peak jitter PHY Clk rise/fall time ISYSCLK/2 40 5 1 4 1 4 1 52 60 5 2 -
8QLW MHz % % ns ns ns ns ns ns ns
UTPHYCLK
RXDATU [15:0], RXPRTYU RXSOCU, RXCLAVU[0] RXENBU[0]
AInput setup to PHY Clk Input hold from PHY Clk
A

P
Input setup to PHY Clk Input hold from PHY Clk Input setup to PHY Clk Input hold from PHY Clk
Data Sheet
6-161
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
7DEOH 1R 80 81 82 83 84
7UDQVPLW 7LPLQJ 'RZQVWUHDP %LW 'DWD %XV 0+] DW &HOO ,QWHUIDFH 6LQJHO 3+< 6LJQDO 1DPH ',5 'HVFULSWLRQ /LPLW 9DOXHV 0LQ 0D[ PHY Clk frequency (nominal) PHY Clk duty cycle PHY Clk peak-to-peak jitter PHY Clk rise/fall time ISYSCLK/2 40 4 52 60 5 2 -
8QLW MHz % % ns ns
UTPHYCLK
TXDATD [15:0], TXSOCD, TXPRTYD, TXENBD[0] TXCLAVD[0]
A>P
Input setup to PHY Clk
85 86 87
Input hold from PHY Clk A

1 4 1
-
ns ns ns
7DEOH 1R 80 81 82 83 84 85 86 87 88 89
5HFHLYH 7LPLQJ 'RZQVWUHDP %LW 'DWD %XV 0+] DW &HOO ,QWHUIDFH 6LQJOH 3+< 6LJQDO 1DPH ',5 'HVFULSWLRQ /LPLW 9DOXHV 0LQ 0D[ ATM Clk frequency (nominal) ATM Clk duty cycle ATM Clk peak-to-peak jitter ATM Clk rise/fall time ISYSCLK/2 40 5 1 4 1 4 1 52 60 5 2 -
8QLW MHz % % ns ns ns ns ns ns ns
UTATMCLK
RXDATD [15:0], RXPRTYD RXSOCD, RXENBD[0] RXCLAVD[0]
A>P
Input setup to ATM Clk Input hold from ATM Clk
A>P AInput setup to ATM Clk Input hold from ATM Clk Input setup from ATM Clk Input hold from ATM Clk
Data Sheet
6-162
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
7DEOH 1R 80 81 82 83 84 85 86 87 86 87 88 89 90 91
7UDQVPLW 7LPLQJ 8SVWUHDP %LW 'DWD %XV 0+] DW &HOO ,QWHUIDFH 0XOWL3+< 6LJQDO 1DPH ',5 'HVFULSWLRQ /LPLW 9DOXHV 0LQ 0D[ UTATMCLK ATM Clk frequency (nominal) ATM Clk duty cycle ATM Clk peak-to-peak jitter ATM Clk rise/fall time TXDATU [15:0], TXSOCU, TXPRTYU TXENBU [3:0], TXADRU [3:0] TXCLAVU [3:0] A

P A

8QLW MHz % % ns ns ns ns ns ns ns ns ns ns ns
Signal going low impedance from 1 ATM Clk Signal going high impedance from ATM Clk 1
Data Sheet
6-163
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
7DEOH 1R 80 81 82 83 84 85 86 87 88 89 90 91 86 87 88 89 90 91
5HFHLYH 7LPLQJ 8SVWUHDP %LW 'DWD %XV 0+] DW &HOO ,QWHUIDFH 0XOWL3+< 6LJQDO 1DPH ',5 'HVFULSWLRQ /LPLW 9DOXHV 0LQ 0D[ PHY Clk frequency (nominal) PHY Clk duty cycle PHY Clk peak-to-peak jitter PHY Clk rise/fall time ISYSCLK/2 40 4 1 5 1 5 0 52 60 5 2 -
8QLW MHz % % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
UTPHYCLK
RXENBU [3:0], RXADRU [3:0] RXDATU [15:0], RXPRTYU
A>P
Input setup to PHY Clk Input hold from PHY Clk
AInput setup to PHY Clk Input hold from PHY Clk Signal going low impedance to PHY Clk Signal going high impedance to PHY Clk
Signal going low impedance from 1 PHY Clk Signal going high impedance from PHY Clk RXSOCU, RXCLAV [3:0] A

Signal going low impedance from 1 PHY Clk Signal going high impedance from PHY Clk 1
Data Sheet
6-164
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
7DEOH 1R 80 81 82 83 84
7UDQVPLW 7LPLQJ 'RZQVWUHDP %LW 'DWD %XV 0+] DW &HOO ,QWHUIDFH 0XOWL3+< 6LJQDO 1DPH ',5 'HVFULSWLRQ /LPLW 9DOXHV 0LQ 0D[ PHY Clk frequency (nominal) PHY Clk duty cycle PHY Clk peak-to-peak jitter PHY Clk rise/fall time ISYSCLK/2 40 4 52 60 5 2 -
8QLW MHz % % ns ns
UTPHYCLK
TXDATD [15:0], TXSOCD, TXPRTYD, TXENBD [3:0], TXADRD [3:0] TXCLAVD [3:0]
A>P
Input setup to PHY Clk
85
Input hold from PHY Clk
1
-
ns
86 87 88 89 90 91
AInput setup to PHY Clk Input hold from PHY Clk Singnal going low impedance to PHY Clk
4 1 4
-
ns ns ns ns ns ns
Singnal going high impedance to 0 PHY Clk Singnal going low impedance from PHY Clk Singnal going high impedance from PHY Clk 1 1
Data Sheet
6-165
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
7DEOH 1R 80 81 82 83 84 85 86 87 88 89 90 91 86 87 88 89 90 91
5HFHLYH 7LPLQJ 'RZQVWUHDP %LW 'DWD %XV 0+] DW &HOO ,QWHUIDFH 0XOWL3+< 6LJQDO 1DPH ',5 'HVFULSWLRQ /LPLW 9DOXHV 0LQ 0D[ ATM Clk frequency (nominal) ATM Clk duty cycle ATM Clk peak-to-peak jitter ATM Clk rise/fall time ISYSCLK/2 40 4 1 5 1 52 60 5 2 -
8QLW MHz % % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
UTATMCLK
RXENBD [3:0] RXADRD [3:0] RXDATD [15:0], RXPRTYD
A>P
Input setup to ATM Clk Input hold from ATM Clk
AInput setup to ATM Clk Input hold from ATM Clk
Singnal going low impedance to 5 ATM Clk Singnal going high impedance to 0 ATM Clk Singnal going low impedance from ATM Clk Singnal going high impedance from ATM Clk RXSOCD, RXCLAVD [3:0] A

Singnal going low impedance to 4 ATM Clk Singnal going high impedance to 0 ATM Clk Singnal going low impedance from ATM Clk Singnal going high impedance from ATM Clk 1 1
Data Sheet
6-166
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
665$0 ,QWHUIDFH Timing of the Synchronous Static RAM Interfaces is simplified as all signals are referenced to the rising edge of SYSCLK. In )LJXUH , it can be seen that all signals output by the PXB 4340 E AOP have identical delay times with reference to the clock. When reading from the RAM, the PXB 4340 E AOP samples the data within a window at the rising clock edge.
100
SYSCLK RSC, RADV, RADR(17:0), RGW, RCE, ROE RDAT(31:0), output
104 101 102
103
RDAT(31:0), input
105 106
)LJXUH
665$0 ,QWHUIDFH *HQHULF 7LPLQJ 'LDJUDP
7DEOH 665$0 ,QWHUIDFH $& 7LPLQJ &KDUDFWHULVWLFV 1R 3DUDPHWHU 0LQ 100 7SYSCLK : Period SYSCLK 19.2 100A 101 102 103 104 105 106 )SYSCLK : Frequency SYSCLK SYSCLK Low Pulse Width SYSCLK High Pulse Width Delay SYSCLK rising to RSC, RADV, RADR(17:0), RGW, RCE, ROE Delay SYSCLK rising to RDAT Output Setup time RDAT Input before SYSCLK rising (read cycles) 7 7 2 2 6
/LPLW 9DOXHV 7\S 0D[ 52
8QLW ns MHz ns ns
15 15
ns ns ns ns
Hold time RDAT Input after SYSCLK rising 1.5 (read cycles)
Data Sheet
6-167
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
&HOO )LOWHU 'HWHFWRU 7LPLQJ
SYSCLK
130 131
FPCT2D, FPCT1D, FPCT2U, FPCT1U
132
)LJXUH
&HOO )LOWHU 'HWHFWRU 7LPLQJ
7DEOH &HOO )LOWHU 'HWHFRU 7LPLQJ 1R 3DUDPHWHU PLQ 130 131 132 Delay SYSCLK high to FPCT active FPCT high time in number of SYSCLK cycles 4 Delay SYSCLK high to FPCT inactive 4
/LPLW 9DOXHV PD[ 15 15 30
8QLW ns ns SYSCLK cycles
Data Sheet
6-168
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
5HVHW 7LPLQJ
power-on
VDD 151 CLK 150 RESET
)LJXUH
5HVHW 7LPLQJ
7DEOH 5HVHW 7LPLQJ 1R 3DUDPHWHU PLQ 150 151 RESET pulse width Number of SYSCLK cycles during RESET active 120 3
/LPLW 9DOXHV PD[
8QLW ns SYSCLK cycles
1RWH
5(6(7 PD\ EH DV\QFKURQRXV WR &/. ZKHQ DVVHUWHG RU GHDVVHUWHG 5(6(7 PD\ EH DVVHUWHG GXULQJ SRZHUXS RU DVVHUWHG DIWHU SRZHUXS 1HYHUWKHOHVV GHDVVHUWLRQ PXVW EH DW D FOHDQ ERXQFHIUHH HGJH
Data Sheet
6-169
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
%RXQGDU\6FDQ 7HVW ,QWHUIDFH
160/ 160A 161 162
TCK
163 164
TMS
165 166
TDI
167/ 167A
TDO
168
TRST
)LJXUH %RXQGDU\6FDQ 7HVW ,QWHUIDFH 7LPLQJ 'LDJUDP
7DEOH %RXQGDU\6FDQ 7HVW ,QWHUIDFH $& 7LPLQJ &KDUDFWHULVWLFV 1R 3DUDPHWHU /LPLW 9DOXHV 0LQ 7\S 0D[ 160 7TCK : Period TCK 100 160A 161 162 163 164 165 166 167 167A 168 )TCK : Frequency TCK TCK high time TCK low time Setup time TMS before TCK rising Hold time TMS after TCK rising Setup time TDI before TCK rising Hold time TDI after TCK rising Delay TCK falling to TDO valid Delay TCK falling to TDO high impedance Pulse width TRST low 200 40 40 10 10 10 10 30 30 10
8QLW ns MHz ns ns ns ns ns ns ns ns ns
Data Sheet
6-170
04.2000
3;% (
(OHFWULFDO &KDUDFWHULVWLFV
&DSDFLWDQFHV
7DEOH &DSDFLWDQFHV 3DUDPHWHU Input Capacitance Output Capacitance Load Capacitance at: UTOPIA Outputs MPDAT(15:0), MPRDY other outputs 3DFNDJH &KDUDFWHULVWLFV
6\PERO PLQ &IN &OUT &FO1 &FO2 &FO3 3 2.5
/LPLW 9DOXHV PD[ 4 4 40 50 20
8QLW pF pF pF pF pF
7DEOH 7KHUPDO 3DFNDJH &KDUDFWHULVWLFV 3DUDPHWHU 7KHUPDO 3DFNDJH 5HVLVWDQFH -XQFWLRQ WR $PELHQW Airflow $PELHQW 7HPSHUDWXUH No airflow Airflow 200 lfpm = 1m/s Airflow 400 lfpm = 2m/s Airflow 600 lfpm = 3m/s 7A=25C 7A=25C 7A=25C 7A=25C
6\PERO
9DOXH
8QLW
RJA(0,25) RJA(0,25) RJA(0,25) RJA(0,25)
17.9 15.7 13.2 12.5
C/W C/W C/W C/W
Data Sheet
6-171
04.2000
3;% (
3DFNDJH 2XWOLQHV
3DFNDJH 2XWOLQHV 3%*$ (Plastic Ball Grid Array)
SMD = Surface Mounted Device
GPA05989
)LJXUH
6RUWV RI 3DFNLQJ
Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device
Data Sheet 7-172
Dimensions in mm
04.2000
3;% (
3DFNDJH 2XWOLQHV
7DEOH 7KHUPDO 5HVLVWDQFH 3DUDPHWHU Junction to case Junction to ambient air without air flow Junction to ambient air with air flow 1.0 m/s Junction to ambient air with air flow 2.0 m/s Junction to ambient air with air flow 3.0 m/s
6\PERO
5thJC 5thJA 5thJA 5thJA 5thJA
/LPLW 9DOXHV 3.0 16.9 14.7 13.7 12.8
8QLW K/W K/W K/W K/W K/W
Data Sheet
7-173
04.2000
3;% (
2YHUYLHZ /LVWV

2YHUYLHZ /LVWV /D\HU 3RLQW &RQILJXUDWLRQV
The following layer points are defined for both F4 and F5 OAM flows: * OEP = Originating End Point (end-to-end OAM cell flow) * TEP = Terminating End Point (end-to-end cell flow) * OSP = Originating Segment Point (segment cell flow) * TSP = Terminating Segment Point (segment cell flow) * IP = Intermediate Point (no origination or termination of OAM flows). The following table gives an overview over all layer points that can be configured in up- and downstream direction of the AOP: 7DEOH
/D\HUSRLQW ) )
/D\HU 3RLQW &RQILJXUDWLRQ
'HILQHG ([WHUQDO 5$0 6HWXS 6&$1 IRU LQWHUQDO 'LUHFWLRQ IODJV 8S 'Q 9&21 ',6 3,3 ',6 &,3 ) ) ) 263 ) 263 (YDO (YDO 763 763 0 x xxx x xxx 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 100 110 101 111 xxx xxx xxx xxx 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 xxx xxx 00x 00x 00x 00x 00x x x x x 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 xxx xxx xxx xxx 100 110 101 111 xxx 100 110 101 111 xxx 100 110 101 111 00x 01x xxx 100 110 101 111 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 /LQNHG OD\HUSW )ORZ )ORZ LQ RSSRVLWH GLUHFWLRQ 0 1 3 2 4 5 7 6 8 21 22 24 23 25 26 27 29 28 30 31 32 9 10 12 11 13
(conn disabled) IP OSP TSP OSP+TSP TEP TEP TEP TEP TEP TEP+TSP TEP+TSP TEP+TSP TEP+TSP TEP+TSP OEP OEP OEP OEP OEP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
invisible invisible invisible invisible IP OSP TSP OSP+TSP IP OSP TSP OSP+TSP IP OSP TSP OSP+TSP OEP OEP+OSP IP OSP TSP OSP+TSP

Data Sheet
8-174
04.2000
3;% (
2YHUYLHZ /LVWV
7DEOH
/D\HUSRLQW )
/D\HU 3RLQW &RQILJXUDWLRQ
'HILQHG ([WHUQDO 5$0 6HWXS IRU 'LUHFWLRQ 8S 'Q 9&21 ',6 3,3 ) 263 763 1 0 01x 1 0 01x 1 0 01x 1 0 01x 1 0 01x 1 1 xxx 1 1 xxx 6&$1 LQWHUQDO IODJV ',6 &,3 ) ) ) 263 (YDO (YDO 763 1 xxx 1 0 0 100 1 1 0 110 1 1 0 101 1 1 0 111 1 1 0 0x0 0 1 0 0x1 0 1 /LQNHG OD\HUSW )ORZ )ORZ LQ RSSRVLWH GLUHFWLRQ 14 15 17 16 18 19 20
)
OEP+OSP OEP+OSP OEP+OSP OEP+OSP OEP+OSP -
IP OSP TSP OSP+TSP TEP TEP+TSP
26 27 28 29 30 31 32
x: no meaning, XVH IRU FRUUHFW RSHUDWLRQ Flows have to be adjusted bidirectionally -> in up- and downstream for each originating point in one direction the terminating point in the other direction has to be adjusted. 2$0 &HOO )RUPDWV 2$0 &HOO +HDGHU &RGLQJ VCI 0003H 0004H 0003H don't care for Rx FFFFH for Tx don't care for Rx FFFFH for Tx don't care for Rx FFFFH for Tx PTI don't care for Rx 000 for Tx don't care for Rx 000 for Tx don't care for Rx 000 for Tx 100 101 100 HK* 111 111 100 111 111 100
F4 Segment flow F4 End-to-end flow F4 Internal Flow (for ICC)* F5 Segment flow F5 End-to-end flow F5 Internal Flow (for ICC)*
* Proprietary functions, use optional
The following sections describe the payload of the OAM cells supported by the AOP. When generating a cell the complete cell is defined, at detection or loop of OAM cells only those fields are given the AOP uses to detect the respective cell. All other fields are handled transparently.
Data Sheet
8-175
04.2000
3;% (
2YHUYLHZ /LVWV
$,6 &HOO *HQHUDWHG $,6 &HOO 10H 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 5HFHLYHG $,6 &HOO 10H 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 000000 : CRC-10(9:0)
3D\ORDG E\WH 3D\ORDG E\WH
E\WH DQG E\WH GRQW FDUH
xxxxxx : CRC-10(9:0)
Data Sheet
8-176
04.2000
3;% (
2YHUYLHZ /LVWV
5', &HOO *HQHUDWHG 5', &HOO 11H 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 5HFHLYHG 5', &HOO 11H 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 000000 : CRC-10(9:0)
3D\ORDG E\WH 3D\ORDG E\WH
E\WH DQG E\WH GRQW FDUH
xxxxxx : CRC-10(9:0)
Data Sheet
8-177
04.2000
3;% (
2YHUYLHZ /LVWV
&& &HOO *HQHUDWHG && &HOO 14H 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 5HFHLYHG && &HOO 14H 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 000000 : CRC-10(9:0)
3D\ORDG E\WH 3D\ORDG E\WH
E\WH DQG E\WH GRQW FDUH
xxxxxx : CRC-10(9:0)
Data Sheet
8-178
04.2000
3;% (
2YHUYLHZ /LVWV
/% &HOO *HQHUDWHG /% &HOO DW RULJLQDWLQJ SRLQW TMR1L(15:8) TMR1L(7:0) TMR2L(15:8) TMR2L(7:0) TMR3L(15:8) TMR3L(7:0) TMR4L(15:8) TMR4L(7:0) TMR5L(15:8) TMR5L(7:0) TMR6L(15:8) TMR6L(7:0) TMR7L(15:8) TMR7L(7:0) TMR8L(15:8) TMR8L(7:0) TMR9L(15:8) TMR9L(7:0) TMR10L(15:8) TMR10L(7:0) TMR11L(15:8) TMR11L(7:0) TMR12L(15:8) TMR12L(7:0) TMR2H(15:8) TMR2H(7:0) TMR3H(15:8) TMR3H(7:0) TMR4H(15:8) TMR4H(7:0) TMR5H(15:8) TMR5H(7:0) TMR6H(15:8) TMR6H(7:0) TMR7H(15:8) TMR7H(7:0) TMR8H(15:8) TMR8H(7:0) TMR9H(15:8) TMR9H(7:0) TMR10H(15:8) TMR10H(7:0) TMR11H(15:8) TMR11H(7:0) TMR12H(15:8) TMR12H(7:0) 000000 : CRC-10(9:0)
3D\ORDG E\WH 3D\ORDG E\WH 3D\ORDG E\WH
TMRxx = Registers for Insertion Buffer access
5HFHLYHG /RRSEDFN &HOO DW ORRSEDFN DQG DW WHUPLQDWLQJ SRLQW 18H 01H Location ID #15 Location ID #14 Location ID #13 Location ID #12 Location ID #11 Location ID #10 Location ID #9 Location ID #8 Location ID #7 Location ID #6 Location ID #5 Location ID #4 Location ID #3 Location ID #2 Location ID #1 Location ID #0 Source ID #15 Source ID #14 Source ID #13 Source ID #12 Source ID #11 Source ID #10 Source ID #9 Source ID #8 Source ID #7 Source ID #6 Source ID #5 Source ID #4 Source ID #3 Source ID #2 Source ID #1 Source ID #0 xxxxxx : CRC-10(9:0) *HQHUDWHG /% &HOO DW ORRSEDFN SRLQW 18H 00H
E\WH DQG E\WH DUH FRSLHG IURP UHFHLYHG /% FHOO
000000 : CRC-10(9:0)
Data Sheet
8-179
04.2000
3;% (
2YHUYLHZ /LVWV
)0 &HOO *HQHUDWHG )0 &HOO 20H BEDC(15:8) FFH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH MCSN BEDC(7:0) FFH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH TUC0+1(15:8) TUC0+1(7:0) TUC0(15:8) TUC0(7:0) FFH FFH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 000000 : CRC-10(9:0)
3D\ORDG E\WH 3D\ORDG E\WH
5HFHLYHG )0 &HOO 20H MCSN BEDC(15:8) BEDC(7:0)
TUC0+1(15:8) TUC0(15:8)
TUC0+1(7:0) TUC0(7:0)
E\WH DQG E\WH GRQW FDUH
xxxxxx : CRC-10(9:0)
Data Sheet
8-180
04.2000
3;% (
2YHUYLHZ /LVWV
%5 &HOO *HQHUDWHG %5 &HOO 21H BEDC(15:8) FFH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH TRCC0+1(15:8) MCSN BEDC(7:0) FFH 6AH 6AH 6AH 6AH 6AH 6AH 6AH TRCC0(15:8) TRCC0+1(7:0) TUC0+1(15:8)* TUC0+1(7:0)* TUC0(15:8)* TUC0(7:0)* FFH FFH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH 6AH TRCC0(7:0) BLER 000000 : CRC-10(9:0)
3D\ORDG E\WH 3D\ORDG E\WH
* TUC0 and TUC0+1 are copied from the received FM cell
5HFHLYHG %5 &HOO 21H MCSN
TUC0+1(15:8) TUC0(15:8)
TUC0+1(7:0)) TUC0(7:0))
E\WH DQG E\WH DQG E\WH GRQW FDUH
TRCC0+1(15:8)
TRCC0(15:8) TRCC0+1(7:0)
TRCC0(7:0) BLER xxxxxx : CRC-10(9:0)
Data Sheet
8-181
04.2000
3;% (
2YHUYLHZ /LVWV
30&& $FWLYDWLRQGHDFWLYDWLRQ &HOO *HQHUDWHG 30&& DFWLYDWLRQGHDFWLYDWLRQ &HOO TMR1L(15:8) TMR1L(7:0) TMR2H(15:8) TMR2H(7:0) TMR2L(15:8) TMR2L(7:0) TMR3H(15:8) TMR3H(7:0) TMR3L(15:8) TMR3L(7:0) TMR4H(15:8) TMR4H(7:0) TMR4L(15:8) TMR4L(7:0) TMR5H(15:8) TMR5H(7:0) TMR5L(15:8) TMR5L(7:0) TMR6H(15:8) TMR6H(7:0) TMR6L(15:8) TMR6L(7:0) TMR7H(15:8) TMR7H(7:0) TMR7L(15:8) TMR7L(7:0) TMR8H(15:8) TMR8H(7:0) TMR8L(15:8) TMR8L(7:0) TMR9H(15:8) TMR9H(7:0) TMR9L(15:8) TMR9L(7:0) TMR10H(15:8) TMR10H(7:0) TMR10L(15:8) TMR10L(7:0) TMR11H(15:8) TMR11H(7:0) TMR11L(15:8) TMR11L(7:0) TMR12H(15:8) TMR12H(7:0) TMR12L(15:8) TMR12L(7:0) 000000 : CRC-10(9:0) 5HFHLYHG DFWLYDWLRQGHDFWLYDWLRQ 30 &HOO DW WHUPLQDWLQJ SRLQW 80H
3D\ORDG E\WH 3D\ORDG E\WH
TMRxx = Registers for Insertion Buffer access
E\WH DQG E\WH DUH GRQW FDUH
xxxxxx : CRC-10(9:0)
Data Sheet
8-182
04.2000
3;% (
2YHUYLHZ /LVWV
3D\ORDG E\WH
5HFHLYHG DFWLYDWLRQGHDFWLYDWLRQ && &HOO DW WHUPLQDWLQJ SRLQW 81H
E\WH DQG E\WH DUH GRQW FDUH
xxxxxx : CRC-10(9:0)
Data Sheet
8-183
04.2000
3;% (
2YHUYLHZ /LVWV
1. 2. 3. 4. 5. 6. 7.
5HIHUHQFHV UTOPIA Level 1 Specification Version 2.01, March 21, 1994, ATM Forum UTOPIA Level 2 Specification Version 1.0, June 1995, ATM Forum IEEE 1596.3 Standard for Low-Voltage Differential Signals for SCI, Draft 1.3, Nov. 95 Joint Test Action Group JTAG standard IEEE Std. 1149.1 `ATM Networks: Concepts, Protocols, Applications', Handel, Schroder, Huber, AddisonWesley, 1994, ISBN 0-201-42274-3 ITU-T Recommendation I.610 B-ISDN Operation and Maintenance Principles and Functions", 11/94 Bellcore TA-NWT 1248 CORE Generic Requirements for Operations of ATM Network Elements" $FURQ\PV
ABM PXB 4330 E $TM %uffer 0anager AIS $larm ,ndication 6ignal (I.610) ALP PXB 4350 E $TM /ayer 3rocessor AOP PXB 4340 E $TM 2AM 3rocessor BEDC %lock (rror 'etection &ode (I.610) BIP-16 %it ,nterleaved 3arity, 16 bit BLER %Oock (rror 5esult (I.610) BR %ackward 5eporting (PM function) byte octet = 8 bit CC &ontinuity &heck (I.610) CLP &ell /oss 3riority of standardized ATM cell CRC-10 &yclic 5edundancy &heck; uses polynomial 1+x+x4+x5+x9+x10 double word 32 bit EDC (rror 'etection &ode of OAM cells (I.610), uses CRC-10 FM )orward 0onitoring (PM cell type) HK +ouse.eeping bits of UDF1 field in UTOPIA cell format HT +eader 7ranslation I/O ,nput / 2utput ICC ,nternal &ontinuity &heck (proprietary I.610) ITU-T ,nternational 7elecommunications 8nion - Telecommunications standardization sector IWE8 PXB 4220 ,nter:orking (lement for 8 channels LB /oopEack (I.610) LCI /ocal &onnection ,dentifier LIC /ine ,nterface &ard or /ine ,nterface &ircuit LOC /oss 2f &ontinuity (I.610) LPS /ine 3rotection 6witching LSB /east 6ignificant %it
Data Sheet
8-184
04.2000
3;% (
2YHUYLHZ /LVWV
octet OAM OEP OSP PM PN PTI RDI SSRAM tbd TEP TM TSP UTOPIA VCVCC VCI VPVPC VPI word
byte = 8 bit 2peration $nd 0aintenance 2riginating (nd 3oint 2riginating 6egment 3oint 3erformance 0onitoring (I.610) 3ort 1umber 3ayload 7ype ,ndication field of standardized ATM cell 5emote 'efect ,ndication (I.610) 6ynchronous 6tatic 5$0 Wo Ee Gefined 7erminating (nd 3oint 7raffic 0anagement 7erminating 6egment 3oint 8niversal 7est and 2Seration ,nterface for $TM 9irtual &hannel specific 9irtual &hannel &onnection 9irtual &hannel ,dentifier of standardized ATM cell 9irtual 3ath specific 9irtual 3ath &onnection 9irtual 3ath ,dentifier of standardized ATM cell 16 bit
Data Sheet
8-185
04.2000

▲Up To Search▲

Price & Availability of PXB4350E

	To Download PXB4350E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .